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/linux-6.8/Documentation/arch/riscv/
Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
6 ISA string ordering in /proc/cpuinfo
7 ------------------------------------
9 The canonical order of ISA extension names in the ISA string is defined in
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
20 #. Additional standard extensions (starting with 'Z') will be sorted after
21 single-letter extensions and before any higher-privileged extensions.
23 #. For additional standard extensions, the first letter following the 'Z'
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/linux-6.8/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.8/arch/riscv/boot/dts/sophgo/
Dsg2042-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
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/linux-6.8/arch/riscv/kernel/
Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "copy-unaligned.h"
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
37 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
41 /* Host ISA bitmap */
44 /* Per-cpu ISA extensions. */
53 * riscv_isa_extension_base() - Get base extension word
55 * @isa_bitmap: ISA bitmap to use
58 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
69 * __riscv_isa_extension_available() - Check whether given extension
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Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
36 return -ENODEV; in riscv_of_processor_hartid()
44 return -ENODEV; in riscv_of_processor_hartid()
51 const char *isa; in riscv_early_of_processor_hartid() local
55 return -ENODEV; in riscv_early_of_processor_hartid()
61 return -ENODEV; in riscv_early_of_processor_hartid()
66 return -ENODEV; in riscv_early_of_processor_hartid()
69 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
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Dsys_hwprobe.c1 // SPDX-License-Identifier: GPL-2.0-only
22 u64 id = -1ULL; in hwprobe_arch_id()
29 switch (pair->key) { in hwprobe_arch_id()
47 * If there's a mismatch for the given set, return -1 in the in hwprobe_arch_id()
51 id = -1ULL; in hwprobe_arch_id()
56 pair->value = id; in hwprobe_arch_id()
65 pair->value = 0; in hwprobe_isa_ext0()
67 pair->value |= RISCV_HWPROBE_IMA_FD; in hwprobe_isa_ext0()
70 pair->value |= RISCV_HWPROBE_IMA_C; in hwprobe_isa_ext0()
73 pair->value |= RISCV_HWPROBE_IMA_V; in hwprobe_isa_ext0()
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/linux-6.8/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux-6.8/arch/riscv/kvm/
Dvcpu_onereg.c1 // SPDX-License-Identifier: GPL-2.0
25 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
27 /* Single letter extensions (alphabetically sorted) */
36 /* Multi letter extensions (alphabetically sorted) */
112 /* Extensions which don't have any mechanism to disable */ in kvm_riscv_vcpu_isa_disable_allowed()
157 /* Extensions which can be disabled using Smstateen */ in kvm_riscv_vcpu_isa_disable_allowed()
175 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
183 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
184 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config()
189 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_config()
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/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux-6.8/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
22 riscv,isa = "rv64imafdc";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.8/arch/riscv/include/asm/
Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define RISCV_ISA_EXT_a ('a' - 'a')
14 #define RISCV_ISA_EXT_c ('c' - 'a')
15 #define RISCV_ISA_EXT_d ('d' - 'a')
16 #define RISCV_ISA_EXT_f ('f' - 'a')
17 #define RISCV_ISA_EXT_h ('h' - 'a')
18 #define RISCV_ISA_EXT_i ('i' - 'a')
19 #define RISCV_ISA_EXT_m ('m' - 'a')
20 #define RISCV_ISA_EXT_q ('q' - 'a')
21 #define RISCV_ISA_EXT_v ('v' - 'a')
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Dcpufeature.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2022-2023 Rivos, Inc
12 #include <asm/alternative-macros.h>
26 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
33 /* Per-cpu ISA extensions. */
127 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_likely()
135 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_unlikely()
/linux-6.8/arch/arm/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 - NEON (Advanced SIMD) extensions
17 tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
25 GCM GHASH function (NIST SP800-38D)
28 - PMULL (Polynomial Multiply Long) instructions
29 - NEON (Advanced SIMD) extensions
30 - ARMv8 Crypto Extensions
34 that is part of the ARMv8 Crypto Extensions, or a slower variant that
35 uses the vmull.p8 instruction that is part of the basic NEON ISA.
45 - NEON (Advanced SIMD) extensions
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/linux-6.8/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
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/linux-6.8/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.8/arch/riscv/
DMakefile2 # architecture-specific flags and dependencies.
9 LDFLAGS_vmlinux := -z norelro
11 LDFLAGS_vmlinux += -shared -Bsymbolic -z notext --emit-relocs
12 KBUILD_CFLAGS += -fPIE
15 LDFLAGS_vmlinux += --no-relax
16 KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
18 CC_FLAGS_FTRACE := -fpatchable-function-entry=4
20 CC_FLAGS_FTRACE := -fpatchable-function-entry=2
25 KBUILD_CFLAGS_MODULE += -mcmodel=medany
33 KBUILD_CFLAGS += -mabi=lp64
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
177 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
184 depends on $(cc-option,-fpatchable-function-entry=8)
187 def_bool $(cc-option,-fsanitize=shadow-call-stack)
188 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
189 depends on $(ld-option,--no-relax-gp)
193 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
196 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
200 # https://github.com/llvm/llvm-project/commit/1df5ea29b43690b6622db2cad7b745607ca4de6a
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/linux-6.8/arch/powerpc/platforms/
DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
283 default "-mtune=power9" if $(cc-option,-mtune=power9)
284 default "-mtune=power8" if $(cc-option,-mtune=power8)
366 This option enables kernel support for larger than 32-bit physical
371 is platform-dependent.
380 This option enables kernel support for the Altivec extensions to the
387 any affect on a non-altivec cpu (it does, however add code to the
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/linux-6.8/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/linux-6.8/arch/x86/events/intel/
Dpt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
8 * http://software.intel.com/en-us/intel-isa-extensions
15 * Single-entry ToPA: when this close to region boundary, switch
54 * struct pt_buffer - buffer configuration; one buffer per task_struct or
93 * struct pt_filter - IP range filter configuration
96 * @config: 4-bit field in RTIT_CTL
105 * struct pt_filters - IP range filtering context
115 * struct pt - per-cpu pt context
/linux-6.8/arch/mips/include/asm/
Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
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