Lines Matching +full:isa +full:- +full:extensions
1 // SPDX-License-Identifier: GPL-2.0
25 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
27 /* Single letter extensions (alphabetically sorted) */
36 /* Multi letter extensions (alphabetically sorted) */
112 /* Extensions which don't have any mechanism to disable */ in kvm_riscv_vcpu_isa_disable_allowed()
157 /* Extensions which can be disabled using Smstateen */ in kvm_riscv_vcpu_isa_disable_allowed()
175 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
183 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
184 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config()
189 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_config()
190 return -EINVAL; in kvm_riscv_vcpu_get_reg_config()
193 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_get_reg_config()
194 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
197 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_get_reg_config()
198 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
202 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_get_reg_config()
203 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
207 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
210 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
213 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
219 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
222 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
223 return -EFAULT; in kvm_riscv_vcpu_get_reg_config()
232 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_config()
233 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_config()
238 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_config()
239 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
241 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_config()
242 return -EFAULT; in kvm_riscv_vcpu_set_reg_config()
245 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_set_reg_config()
248 * single letter extensions. in kvm_riscv_vcpu_set_reg_config()
251 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
257 if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) in kvm_riscv_vcpu_set_reg_config()
260 if (!vcpu->arch.ran_atleast_once) { in kvm_riscv_vcpu_set_reg_config()
261 /* Ignore the enable/disable request for certain extensions */ in kvm_riscv_vcpu_set_reg_config()
276 /* Do not modify anything beyond single letter extensions */ in kvm_riscv_vcpu_set_reg_config()
277 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | in kvm_riscv_vcpu_set_reg_config()
279 vcpu->arch.isa[0] = reg_val; in kvm_riscv_vcpu_set_reg_config()
282 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
286 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_set_reg_config()
287 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
289 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
292 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_set_reg_config()
293 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
295 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
298 if (reg_val == vcpu->arch.mvendorid) in kvm_riscv_vcpu_set_reg_config()
300 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
301 vcpu->arch.mvendorid = reg_val; in kvm_riscv_vcpu_set_reg_config()
303 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
306 if (reg_val == vcpu->arch.marchid) in kvm_riscv_vcpu_set_reg_config()
308 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
309 vcpu->arch.marchid = reg_val; in kvm_riscv_vcpu_set_reg_config()
311 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
314 if (reg_val == vcpu->arch.mimpid) in kvm_riscv_vcpu_set_reg_config()
316 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
317 vcpu->arch.mimpid = reg_val; in kvm_riscv_vcpu_set_reg_config()
319 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
323 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
326 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
335 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_get_reg_core()
337 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_core()
338 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_core()
343 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_core()
344 return -EINVAL; in kvm_riscv_vcpu_get_reg_core()
346 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
349 reg_val = cntx->sepc; in kvm_riscv_vcpu_get_reg_core()
354 reg_val = (cntx->sstatus & SR_SPP) ? in kvm_riscv_vcpu_get_reg_core()
357 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
359 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_core()
360 return -EFAULT; in kvm_riscv_vcpu_get_reg_core()
368 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_set_reg_core()
370 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_core()
371 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_core()
376 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_core()
377 return -EINVAL; in kvm_riscv_vcpu_set_reg_core()
379 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
381 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_core()
382 return -EFAULT; in kvm_riscv_vcpu_set_reg_core()
385 cntx->sepc = reg_val; in kvm_riscv_vcpu_set_reg_core()
391 cntx->sstatus |= SR_SPP; in kvm_riscv_vcpu_set_reg_core()
393 cntx->sstatus &= ~SR_SPP; in kvm_riscv_vcpu_set_reg_core()
395 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
404 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_get_csr()
407 return -ENOENT; in kvm_riscv_vcpu_general_get_csr()
411 *out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; in kvm_riscv_vcpu_general_get_csr()
412 *out_val |= csr->hvip & ~IRQ_LOCAL_MASK; in kvm_riscv_vcpu_general_get_csr()
423 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_set_csr()
426 return -ENOENT; in kvm_riscv_vcpu_general_set_csr()
436 WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0); in kvm_riscv_vcpu_general_set_csr()
445 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_set_csr()
449 return -EINVAL; in kvm_riscv_vcpu_smstateen_set_csr()
459 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_get_csr()
463 return -EINVAL; in kvm_riscv_vcpu_smstateen_get_csr()
474 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_csr()
475 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_csr()
480 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_csr()
481 return -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
493 rc = -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
499 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_csr()
505 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_csr()
506 return -EFAULT; in kvm_riscv_vcpu_get_reg_csr()
516 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_csr()
517 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_csr()
522 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_csr()
523 return -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
525 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_csr()
526 return -EFAULT; in kvm_riscv_vcpu_set_reg_csr()
538 rc = -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
544 rc = -ENOENT; in kvm_riscv_vcpu_set_reg_csr()
561 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
565 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
568 if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) in riscv_vcpu_get_isa_ext_single()
582 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
586 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
588 if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa)) in riscv_vcpu_set_isa_ext_single()
591 if (!vcpu->arch.ran_atleast_once) { in riscv_vcpu_set_isa_ext_single()
593 * All multi-letter extension and a few single letter in riscv_vcpu_set_isa_ext_single()
598 set_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
601 clear_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
603 return -EINVAL; in riscv_vcpu_set_isa_ext_single()
606 return -EBUSY; in riscv_vcpu_set_isa_ext_single()
619 return -ENOENT; in riscv_vcpu_get_isa_ext_multi()
642 return -ENOENT; in riscv_vcpu_set_isa_ext_multi()
660 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_isa_ext()
661 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_isa_ext()
666 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_isa_ext()
667 return -EINVAL; in kvm_riscv_vcpu_get_reg_isa_ext()
684 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_isa_ext()
689 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_isa_ext()
690 return -EFAULT; in kvm_riscv_vcpu_get_reg_isa_ext()
699 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_isa_ext()
700 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_isa_ext()
705 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_isa_ext()
706 return -EINVAL; in kvm_riscv_vcpu_set_reg_isa_ext()
711 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_isa_ext()
712 return -EFAULT; in kvm_riscv_vcpu_set_reg_isa_ext()
722 return -ENOENT; in kvm_riscv_vcpu_set_reg_isa_ext()
743 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in copy_config_reg_indices()
746 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in copy_config_reg_indices()
754 return -EFAULT; in copy_config_reg_indices()
785 return -EFAULT; in copy_core_reg_indices()
797 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) in num_csr_regs()
799 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) in num_csr_regs()
820 return -EFAULT; in copy_csr_reg_indices()
826 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) { in copy_csr_reg_indices()
837 return -EFAULT; in copy_csr_reg_indices()
844 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) { in copy_csr_reg_indices()
855 return -EFAULT; in copy_csr_reg_indices()
879 return -EFAULT; in copy_timer_reg_indices()
889 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_f_regs()
891 if (riscv_isa_extension_available(vcpu->arch.isa, f)) in num_fp_f_regs()
892 return sizeof(cntx->fp.f) / sizeof(u32); in num_fp_f_regs()
908 return -EFAULT; in copy_fp_f_reg_indices()
918 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_d_regs()
920 if (riscv_isa_extension_available(vcpu->arch.isa, d)) in num_fp_d_regs()
921 return sizeof(cntx->fp.d.f) / sizeof(u64) + 1; in num_fp_d_regs()
934 for (i = 0; i < n-1; i++) { in copy_fp_d_reg_indices()
940 return -EFAULT; in copy_fp_d_reg_indices()
949 return -EFAULT; in copy_fp_d_reg_indices()
973 return -EFAULT; in copy_isa_ext_reg_indices()
1003 return -EFAULT; in copy_sbi_ext_reg_indices()
1020 struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; in copy_sbi_reg_indices()
1023 if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] == KVM_RISCV_SBI_EXT_STATUS_ENABLED) { in copy_sbi_reg_indices()
1034 return -EFAULT; in copy_sbi_reg_indices()
1052 if (!riscv_isa_extension_available(vcpu->arch.isa, v)) in num_vector_regs()
1062 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in copy_vector_reg_indices()
1077 return -EFAULT; in copy_vector_reg_indices()
1083 size = __builtin_ctzl(cntx->vector.vlenb); in copy_vector_reg_indices()
1091 return -EFAULT; in copy_vector_reg_indices()
1100 * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
1123 * kvm_riscv_vcpu_copy_reg_indices - get indices of all registers.
1186 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_set_reg()
1213 return -ENOENT; in kvm_riscv_vcpu_set_reg()
1219 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_get_reg()
1246 return -ENOENT; in kvm_riscv_vcpu_get_reg()