| /linux-3.3/arch/sparc/kernel/ |
| D | iommu.c | 1 /* iommu.c: Generic sparc64 IOMMU support.
14 #include <linux/iommu-helper.h>
21 #include <asm/iommu.h>
46 /* Must be invoked under the IOMMU lock. */
47 static void iommu_flushall(struct iommu *iommu) in iommu_flushall() argument
49 if (iommu->iommu_flushinv) { in iommu_flushall()
50 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
55 tag = iommu->iommu_tags; in iommu_flushall()
62 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
76 #define IOPTE_IS_DUMMY(iommu, iopte) \ argument
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| D | pci_sun4v.c | 19 #include <asm/iommu.h>
39 unsigned long prot; /* IOMMU page protections */
76 printk("iommu_batch_flush: IOMMU map of " in iommu_batch_flush()
134 struct iommu *iommu; in dma_4v_alloc_coherent() local
155 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
157 spin_lock_irqsave(&iommu->lock, flags); in dma_4v_alloc_coherent()
158 entry = iommu_range_alloc(dev, iommu, npages, NULL); in dma_4v_alloc_coherent()
159 spin_unlock_irqrestore(&iommu->lock, flags); in dma_4v_alloc_coherent()
164 *dma_addrp = (iommu->page_table_map_base + in dma_4v_alloc_coherent()
191 spin_lock(&iommu->lock); in dma_4v_alloc_coherent()
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| D | sbus.c | 34 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
36 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
39 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
60 struct iommu *iommu = dev->archdata.iommu; in sbus_set_sbus64() local
75 cfg_reg = iommu->write_complete_reg; in sbus_set_sbus64()
210 struct iommu *iommu = op->dev.archdata.iommu; in sbus_build_irq() local
211 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq()
272 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ue_handler() local
273 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler()
346 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ce_handler() local
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| D | psycho_common.c | 181 printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) " in psycho_dump_iommu_tags_and_data()
188 printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) " in psycho_dump_iommu_tags_and_data()
206 struct iommu *iommu = pbm->iommu; in psycho_check_iommu_error() local
209 spin_lock_irqsave(&iommu->lock, flags); in psycho_check_iommu_error()
210 control = upa_readq(iommu->iommu_control); in psycho_check_iommu_error()
215 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
232 printk(KERN_ERR "%s: IOMMU Error, type[%s]\n", in psycho_check_iommu_error()
245 spin_unlock_irqrestore(&iommu->lock, flags); in psycho_check_iommu_error()
402 struct iommu *iommu = pbm->iommu; in psycho_iommu_init() local
406 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; in psycho_iommu_init()
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| D | iommu_common.h | 1 /* iommu_common.h: UltraSparc SBUS/PCI common iommu declarations.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu.h>
21 * These give mapping size of each iommu pte/tlb.
52 struct iommu *iommu,
55 extern void iommu_range_free(struct iommu *iommu,
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| D | pci_fire.c | 30 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
42 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
43 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
44 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
45 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
50 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
55 upa_writeq(~(u64)0, iommu->iommu_flushinv); in pci_fire_pbm_iommu_init()
57 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, in pci_fire_pbm_iommu_init()
62 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase); in pci_fire_pbm_iommu_init()
64 control = upa_readq(iommu->iommu_control); in pci_fire_pbm_iommu_init()
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| /linux-3.3/drivers/iommu/ |
| D | amd_iommu_init.c | 27 #include <linux/amd-iommu.h>
30 #include <asm/iommu.h>
82 * structure describing one IOMMU in the ACPI table. Typically followed by one
98 * A device entry describing which devices a specific IOMMU translates and
109 * An AMD IOMMU memory definition structure. It defines things like exclusion
172 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * The rlookup table is used to find the IOMMU which is responsible
184 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
195 * the IOMMU used by this driver.
197 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
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| D | intr_remapping.c | 12 #include <linux/intel-iommu.h>
77 *entry = *(irq_iommu->iommu->ir_table->base + index); in get_irte()
83 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) in alloc_irte() argument
85 struct ir_table *table = iommu->ir_table; in alloc_irte()
105 if (mask > ecap_max_handle_mask(iommu->ecap)) { in alloc_irte()
109 ecap_max_handle_mask(iommu->ecap)); in alloc_irte()
134 irq_iommu->iommu = iommu; in alloc_irte()
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) in qi_flush_iec() argument
152 return qi_submit_sync(&desc, iommu); in qi_flush_iec()
171 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) in set_irte_irq() argument
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| D | dmar.c | 32 #include <linux/intel-iommu.h>
234 drhd->iommu->node = node; in dmar_parse_one_rhsa()
525 printk("IOMMU: can't validate: %llx\n", drhd->address); in check_zero_address()
571 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
583 struct intel_iommu *iommu; in alloc_iommu() local
595 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in alloc_iommu()
596 if (!iommu) in alloc_iommu()
599 iommu->seq_id = iommu_allocated++; in alloc_iommu()
600 sprintf (iommu->name, "dmar%d", iommu->seq_id); in alloc_iommu()
602 iommu->reg = ioremap(drhd->reg_base_addr, VTD_PAGE_SIZE); in alloc_iommu()
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| D | intel-iommu.c | 38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
46 #include <asm/iommu.h>
84 * to the IOMMU core, which will then use this information to split
88 * Traditionally the IOMMU core just handed us the mappings directly,
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
165 /* global iommu list, set NULL for ignored DMAR units */
342 * 2. It maps to each iommu if successful.
343 * 3. Each iommu mapps to this domain if successful.
375 int iommu_coherency;/* indicate coherency of iommu access */
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| D | Kconfig | 6 bool "IOMMU Hardware Support"
16 # MSM IOMMU support
18 bool "MSM IOMMU Support"
32 # AMD IOMMU support
34 bool "AMD IOMMU support"
43 With this option you can enable support for AMD IOMMU hardware in
44 your system. An IOMMU is a hardware component which provides
45 remapping of DMA memory accesses from devices. With an AMD IOMMU you
49 You can find out if your system has an AMD IOMMU if you look into
54 bool "Export AMD IOMMU statistics to debugfs"
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| D | amd_iommu.c | 28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
31 #include <linux/amd-iommu.h>
36 #include <asm/iommu.h>
49 * to the IOMMU core, which will then use this information to split
53 * Traditionally the IOMMU core just handed us the mappings directly,
60 * If at some point we'd like to utilize the IOMMU core's new behavior,
77 * if iommu=pt passed on kernel cmd line.
87 * general struct to manage commands send to an IOMMU
172 return dev->archdata.iommu; in get_dev_data()
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| D | omap-iommu.c | 2 * omap iommu: tlb and pagetable primitives
21 #include <linux/iommu.h>
27 #include <plat/iommu.h>
40 * struct omap_iommu_domain - omap iommu domain
42 * @iommu_dev: an omap iommu device attached to this domain. only a single
43 * iommu device can be attached for now.
59 * omap_install_iommu_arch - Install archtecure specific iommu functions
60 * @ops: a pointer to architecture specific iommu functions
62 * There are several kind of iommu algorithm(tlb, pagetable) among
63 * omap series. This interface installs such an iommu algorighm.
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| D | amd_iommu_types.h | 40 /* Length of the MMIO region for the AMD IOMMU */
60 /* Flag masks for the AMD IOMMU exclusion range */
258 * Creates an IOMMU PTE for an address an a given pagesize
307 /* IOMMU capabilities */
320 domain for an IOMMU */
340 #define for_each_iommu(iommu) \ argument
341 list_for_each_entry((iommu), &amd_iommu_list, list)
342 #define for_each_iommu_safe(iommu, next) \ argument
343 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
376 * This structure contains generic data for IOMMU protection domains
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| D | iommu.c | 28 #include <linux/iommu.h>
86 * bus_set_iommu - set iommu-callbacks for the bus
88 * @ops: the callbacks provided by the iommu-driver
90 * This function is called by an iommu driver to set the iommu methods
92 * the iommu-api after these ops are registered.
94 * the bus itself, so the iommu drivers are not initialized when the bus
95 * is set up. With this function the iommu-driver can set the iommu-ops
105 /* Do IOMMU specific setup for this bus-type */ in bus_set_iommu()
119 * iommu_set_fault_handler() - set a fault handler for an iommu domain
120 * @domain: iommu domain
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| /linux-3.3/arch/powerpc/platforms/cell/ |
| D | iommu.c | 2 * IOMMU implementation for Cell Broadband Processor Architecture
35 #include <asm/iommu.h>
105 /* IOMMU sizing */
114 struct cbe_iommu *iommu; member
141 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
148 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
205 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
228 __pa(window->iommu->pad_page) | in tce_free_cell()
239 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
245 struct cbe_iommu *iommu = data; in ioc_interrupt() local
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| /linux-3.3/arch/sparc/mm/ |
| D | iommu.c | 2 * iommu.c: IOMMU specific routines for memory management.
27 #include <asm/iommu.h>
61 struct iommu_struct *iommu; in sbus_iommu_init() local
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
67 if (!iommu) { in sbus_iommu_init()
68 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
74 if (!iommu->regs) { in sbus_iommu_init()
75 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
78 impl = (iommu->regs->control & IOMMU_CTRL_IMPL) >> 28; in sbus_iommu_init()
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| /linux-3.3/arch/arm/mach-msm/include/mach/ |
| D | iommu.h | 24 /* Sharability attributes of MSM IOMMU mappings */
28 /* Cacheability attributes of MSM IOMMU mappings */
46 * struct msm_iommu_dev - a single IOMMU hardware instance
47 * name Human-readable name given to this IOMMU HW instance
48 * ncb Number of context banks present on this IOMMU HW instance
56 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
72 * struct msm_iommu_drvdata - A single IOMMU hardware instance
73 * @base: IOMMU config port base address (VA)
74 * @ncb The number of contexts on this IOMMU
76 * @clk: The bus clock for this IOMMU hardware instance
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| /linux-3.3/Documentation/x86/x86_64/ |
| D | boot-options.txt | 201 IOMMU (input/output memory management unit)
205 1. <arch/x86_64/kernel/pci-nommu.c>: use no hardware/software IOMMU at all
207 Kernel boot message: "PCI-DMA: Disabling IOMMU"
209 2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
210 Kernel boot message: "PCI-DMA: using GART IOMMU"
212 3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
213 e.g. if there is no hardware IOMMU in the system and it is need because
214 you have >3GB memory or told the kernel to us it (iommu=soft))
218 4. <arch/x86_64/pci-calgary.c> : IBM Calgary hardware IOMMU. Used in IBM
219 pSeries and xSeries servers. This hardware IOMMU supports DMA address
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| /linux-3.3/arch/arm/plat-omap/include/plat/ |
| D | iommu.h | 2 * omap iommu: main structures
42 * but share it globally for each iommu.
52 void *ctx; /* iommu context: registres saved area */
115 * struct iommu_arch_data - omap iommu private data
116 * @name: name of the iommu device
117 * @iommu_dev: handle of the iommu device
119 * This is an omap iommu private data object, which binds an iommu user
120 * to its iommu device. This object should be placed at the iommu user's
121 * dev_archdata so generic IOMMU API can be used without having to
130 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
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| /linux-3.3/include/linux/ |
| D | iommu.h | 33 /* iommu fault flags */
52 * struct iommu_ops - iommu ops and capabilities
53 * @domain_init: init iommu domain
54 * @domain_destroy: destroy iommu domain
55 * @attach_dev: attach device to an iommu domain
56 * @detach_dev: detach device from an iommu domain
57 * @map: map a physically contiguous memory region to an iommu domain
58 * @unmap: unmap a physically contiguous memory region from an iommu domain
61 * @commit: commit iommu domain
102 * report_iommu_fault() - report about an IOMMU fault to the IOMMU framework
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| D | dma_remapping.h | 30 extern void free_dmar_iommu(struct intel_iommu *iommu);
31 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
32 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
36 static inline int iommu_calculate_agaw(struct intel_iommu *iommu) in iommu_calculate_agaw() argument
40 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) in iommu_calculate_max_sagaw() argument
44 static inline void free_dmar_iommu(struct intel_iommu *iommu) in free_dmar_iommu() argument
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| D | intel-iommu.h | 30 #include <asm/iommu.h>
33 * Intel IOMMU register specification per version 1.0 public spec.
36 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
215 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ argument
219 sts = op(iommu->reg + offset); \
295 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
297 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
315 int seq_id; /* sequence id of the iommu */
316 int agaw; /* agaw of this iommu */
317 int msagaw; /* max sagaw of this iommu */
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| /linux-3.3/arch/sparc/include/asm/ |
| D | iommu_32.h | 1 /* iommu.h: Definitions for the sun4m IOMMU.
11 /* The iommu handles all virtual to physical address translations
14 * translated by the on chip SRMMU. The iommu and the srmmu do
17 * Basically the iommu handles all dvma sbus activity.
20 /* The IOMMU registers occupy three pages in IO space. */
23 volatile unsigned long control; /* IOMMU control */
41 volatile unsigned long mid; /* IOMMU module-id */
55 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
66 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
71 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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| D | iommu_64.h | 1 /* iommu.h: Definitions for the sun5 IOMMU.
26 struct iommu { struct
29 void (*flush_all)(struct iommu *); argument
61 extern int iommu_table_init(struct iommu *iommu, int tsbsize, argument
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