include/linux/intel-iommu.h

30 #include <asm/iommu.h>
33  * Intel IOMMU register specification per version 1.0 public spec.
36 #define	DMAR_VER_REG	0x0	/* Arch version supported by this IOMMU */
215 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)			\  argument
219 		sts = op(iommu->reg + offset);				\
295 	void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
297 	void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
315 	int		seq_id;	/* sequence id of the iommu */
316 	int		agaw; /* agaw of this iommu */
317 	int		msagaw; /* max sagaw of this iommu */
330 	u32 *iommu_state; /* Store iommu states between suspend and resume.*/
339 	struct intel_iommu *iommu, void *addr, int size)  in __iommu_flush_cache()  argument
341 	if (!ecap_coherent(iommu->ecap))  in __iommu_flush_cache()
349 extern void free_iommu(struct intel_iommu *iommu);
350 extern int dmar_enable_qi(struct intel_iommu *iommu);
351 extern void dmar_disable_qi(struct intel_iommu *iommu);
352 extern int dmar_reenable_qi(struct intel_iommu *iommu);
353 extern void qi_global_iec(struct intel_iommu *iommu);
355 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
357 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
359 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
362 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);