Searched +full:interrupts +full:- +full:extended (Results 1 – 6 of 6) sorted by relevance
16 #define CR_P (1 << 4) /* 32-bit exception handler */17 #define CR_D (1 << 5) /* 32-bit data address range */34 #define CR_XP (1 << 23) /* Extended page tables */35 #define CR_VE (1 << 24) /* Vectored interrupts */
4 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.75 #define PRE_OVERFLOW2_32 (ALL_SET_32 - COUNT - MARGIN)76 #define PRE_OVERFLOW2_64 (ALL_SET_64 - COUNT - MARGIN)94 uint32_t interrupts[32]; member181 /* disable overflow interrupts on all counters */ in pmu_reset()260 * The low 32-bits of PMCEID0/1 respectively describe in is_event_supported()261 * event support for events 0-31/32-63. Their High in is_event_supported()262 * 32-bits describe support for extended events in is_event_supported()347 pmu_stats.interrupts[i]++; in irq_handler()364 pmu_stats.interrupts[i] = 0; in pmu_reset_stats()[all …]
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>42 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */50 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */113 /* 0x35-0x3b are reserved */119 /* Header type 1 (PCI-to-PCI bridges) */147 /* 0x35-0x3b is reserved */149 /* 0x3c-0x3d are same as for htype 0 */180 /* 0x3c-0x3d are same as for htype 0 */188 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */194 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */[all …]
18 * Get a linear address by combining @addr with a non-canonical pattern in the239 * Each X86_FEATURE_XXX definition is 64-bit and contains the following240 * CPUID meta-data:296 * Extended Leafs, a.k.a. AMD defined445 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests770 * Enable interrupts and ensure that interrupts are evaluated upon return from779 * Enable interrupts for one instruction (nop), to allow the CPU to process all780 * interrupts that are already pending.912 int shift_amt = 64 - va_width; in is_canonical()972 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. in generate_usermode_ac()[all …]
51 int pos = -1; in ffs()156 if (((rdtsc() - tsc_val) >> preempt_scale) in preemption_timer_main()183 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, in preemption_timer_exit_handler()184 "busy-wait for preemption timer"); in preemption_timer_exit_handler()191 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val in preemption_timer_exit_handler()228 report_fail("busy-wait for preemption timer"); in preemption_timer_exit_handler()659 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); in iobmp_main()664 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); in iobmp_main()667 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); in iobmp_main()670 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); in iobmp_main()[all …]
46 return vmcb->control.exit_code == SVM_EXIT_VMMCALL; in null_check()51 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMRUN); in prepare_no_vmrun_int()56 return vmcb->control.exit_code == SVM_EXIT_ERR; in check_no_vmrun_int()66 return vmcb->control.exit_code == SVM_EXIT_VMRUN; in check_vmrun()72 vmcb->control.intercept |= 1 << INTERCEPT_RSM; in prepare_rsm_intercept()73 vmcb->control.intercept_exceptions |= (1ULL << UD_VECTOR); in prepare_rsm_intercept()90 if (vmcb->control.exit_code != SVM_EXIT_RSM) { in finished_rsm_intercept()92 vmcb->control.exit_code); in finished_rsm_intercept()95 vmcb->control.intercept &= ~(1 << INTERCEPT_RSM); in finished_rsm_intercept()100 if (vmcb->control.exit_code != SVM_EXIT_EXCP_BASE + UD_VECTOR) { in finished_rsm_intercept()[all …]