| /qemu/hw/ssi/ |
| H A D | stm32f2xx_spi.c | 79 qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n", in stm32f2xx_spi_read()
89 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
93 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
97 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
101 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
105 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
130 "Interrupts and DMA are not implemented\n", __func__); in stm32f2xx_spi_write()
143 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__); in stm32f2xx_spi_write()
155 "I2S is not implemented\n", __func__); in stm32f2xx_spi_write()
159 "I2S is not implemented\n", __func__); in stm32f2xx_spi_write()
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| H A D | pl022.c | 153 /* Not implemented. */ in pl022_read()
177 BADF("SPI peripheral mode not implemented\n"); in pl022_write()
208 qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n"); in pl022_write()
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| /qemu/hw/adc/ |
| H A D | stm32f2xx_adc.c | 128 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_read()
143 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_read()
151 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_read()
206 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_write()
227 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_write()
236 "Injection ADC is not implemented, the registers are " \ in stm32f2xx_adc_write()
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| /qemu/hw/misc/ |
| H A D | stm32l4x5_rcc.c | 377 * TODO: Handle LSECSSF and CSSF flags when the CSS is implemented. in rcc_update_irq()
902 /* Reset flags: Not implemented */ in rcc_update_csr()
903 /* MSISRANGE: Not implemented after reset */ in rcc_update_csr()
1092 "%s: Side-effects not implemented for ICSCR\n", __func__); in stm32l4x5_rcc_write()
1113 "%s: Side-effects not implemented for CIER\n", __func__); in stm32l4x5_rcc_write()
1125 /* Reset behaviors are not implemented */ in stm32l4x5_rcc_write()
1129 "%s: Side-effects not implemented for AHB1RSTR\n", __func__); in stm32l4x5_rcc_write()
1134 "%s: Side-effects not implemented for AHB2RSTR\n", __func__); in stm32l4x5_rcc_write()
1139 "%s: Side-effects not implemented for AHB3RSTR\n", __func__); in stm32l4x5_rcc_write()
1144 "%s: Side-effects not implemented for APB1RSTR1\n", __func__); in stm32l4x5_rcc_write()
[all …]
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| /qemu/hw/net/ |
| H A D | smc91c111.c | 475 /* Not implemented. */ in smc91c111_writeb()
486 "smc91c111: EEPROM store not implemented\n"); in smc91c111_writeb()
490 "smc91c111: EEPROM reload not implemented\n"); in smc91c111_writeb()
593 /* Not implemented. */ in smc91c111_writeb()
596 /* Not implemented. */ in smc91c111_writeb()
639 /* Not implemented. */ in smc91c111_readb()
655 /* Not implemented. */ in smc91c111_readb()
669 /* Not implemented. */ in smc91c111_readb()
736 /* Not implemented. */ in smc91c111_readb()
739 /* Not implemented. */ in smc91c111_readb()
[all …]
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| H A D | lan9118_phy.c | 77 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", in lan9118_phy_read()
125 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", in lan9118_phy_write()
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| /qemu/target/mips/tcg/system/ |
| H A D | cp0_helper.c | 544 * Yield scheduler intercept not implemented. in helper_mtc0_vpecontrol()
545 * Gating storage scheduler intercept not implemented. in helper_mtc0_vpecontrol()
627 /* UDI not implemented. */ in helper_mtc0_vpeconf1()
628 /* CP2 not implemented. */ in helper_mtc0_vpeconf1()
637 /* Yield qualifier inputs not implemented. */ in helper_mtc0_yqmask()
650 /* 1k pages not implemented */ in helper_mtc0_entrylo0()
727 /* MIPS16 not implemented. */ in helper_mtc0_tcrestart()
740 /* MIPS16 not implemented. */ in helper_mttc0_tcrestart()
746 /* MIPS16 not implemented. */ in helper_mttc0_tcrestart()
838 /* 1k pages not implemented */ in helper_mtc0_entrylo1()
[all …]
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| /qemu/target/arm/ |
| H A D | idau.h | 21 * typically implemented in the SoC which provides board or SoC
24 * QOM interface which is implemented by the board or SoC object and
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| /qemu/include/qemu/ |
| H A D | module.h | 112 * dependencies and QOM objects implemented by modules.
151 * restricted. Use case example: the ccw bus is implemented by s390x
170 * This module requires a core module that should be implemented and
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| H A D | target-info.h | 29 * Returns: Name of the QOM interface implemented by machines
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| /qemu/hw/ppc/ |
| H A D | pnv_adu.c | 51 qemu_log_mask(LOG_UNIMP, "ADU: LPC_BASE_REG is not implemented\n"); in pnv_adu_xscom_read()
109 "ADU: Changing LPC_BASE_REG is not implemented\n"); in pnv_adu_xscom_write()
157 "ADU: Changing LPC_STATUS_REG is not implemented\n"); in pnv_adu_xscom_write()
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| /qemu/target/ppc/translate/ |
| H A D | processor-ctrl-impl.c.inc | 29 * implemented in the "Embedded.Processor Control" category.
53 * implemented in the "Embedded.Processor Control" category.
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| /qemu/include/hw/intc/ |
| H A D | arm_gicv3_common.h | 33 * Note that this does not include LPIs. When implemented, these should be
92 * In the state struct they are implemented as a 3-element array which
176 * If the number of implemented list registers is 0 then the
177 * virtualization support is not implemented.
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| /qemu/hw/gpio/ |
| H A D | bcm2838_gpio.c | 213 /* Not implemented */ in bcm2838_gpio_read()
214 qemu_log_mask(LOG_UNIMP, "%s: %s: not implemented for %"HWADDR_PRIx"\n", in bcm2838_gpio_read()
281 /* Not implemented */ in bcm2838_gpio_write()
282 qemu_log_mask(LOG_UNIMP, "%s: %s: not implemented for %"HWADDR_PRIx"\n", in bcm2838_gpio_write()
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| /qemu/hw/acpi/ |
| H A D | tpm.c | 297 * 3: Not implemented in tpm_build_ppi_acpi()
301 /* 3 = not implemented */ in tpm_build_ppi_acpi()
316 * 1: Not Implemented in tpm_build_ppi_acpi()
336 /* 1: not implemented */ in tpm_build_ppi_acpi()
385 * 0: Not implemented in tpm_build_ppi_acpi()
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| /qemu/docs/interop/ |
| H A D | dbus.rst | 44 methods implemented using D-Bus are just as critical. Peers need to
104 The "org.qemu.*" prefix is reserved for services implemented &
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| /qemu/hw/intc/ |
| H A D | rx_icu.c | 213 "not implemented.\n", in icu_read()
240 qemu_log_mask(LOG_UNIMP, "rx_icu: DTC not implemented\n"); in icu_write()
261 qemu_log_mask(LOG_UNIMP, "rx_icu: DMAC not implemented\n"); in icu_write()
280 "not implemented\n", in icu_write()
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| H A D | pl190.c | 20 if implemented. */
198 /* TODO: Protection (supervisor only access) is not implemented. */ in pl190_write()
212 qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n"); in pl190_write()
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| /qemu/hw/net/rocker/ |
| H A D | rocker.c | 196 qemu_log_mask(LOG_UNIMP, "rocker %s: L3 not implemented" in tx_consume()
203 qemu_log_mask(LOG_UNIMP, "rocker %s: TSO not implemented (MSS: %u)\n", in tx_consume()
209 qemu_log_mask(LOG_UNIMP, "rocker %s: TSO not implemented" in tx_consume()
813 DPRINTF("not implemented dma reg write(l) addr=0x" HWADDR_FMT_plx in rocker_io_writel()
855 DPRINTF("not implemented write(l) addr=0x" HWADDR_FMT_plx in rocker_io_writel()
874 DPRINTF("not implemented dma reg write(q) addr=0x" HWADDR_FMT_plx in rocker_io_writeq()
893 DPRINTF("not implemented write(q) addr=0x" HWADDR_FMT_plx in rocker_io_writeq()
1058 DPRINTF("not implemented dma reg read(l) addr=0x" HWADDR_FMT_plx in rocker_io_readl()
1113 DPRINTF("not implemented read(l) addr=0x" HWADDR_FMT_plx "\n", addr); in rocker_io_readl()
1134 DPRINTF("not implemented dma reg read(q) addr=0x" HWADDR_FMT_plx in rocker_io_readq()
[all …]
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| /qemu/target/mips/ |
| H A D | cpu-defs.c.inc | 36 /* Have config3, no tertiary/secondary caches implemented */
81 /* Config1 implemented, fixed mapping MMU,
217 /* No DSP implemented. */
261 /* No DSP implemented. */
375 /* Config1 implemented, fixed mapping MMU,
1041 /* MVPConf1 implemented, TLB shareable, no gating storage support,
1042 programmable cache partitioning implemented, number of allocatable
1044 implemented, 5 TCs implemented. */
1058 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
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| /qemu/include/hw/pci/ |
| H A D | pci_device.h | 14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
19 /* Implemented by devices that can be plugged on PCI Express buses */
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
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| /qemu/hw/timer/ |
| H A D | bcm2835_systmr.c | 11 * Only the free running 64-bit counter is implemented.
12 * The 4 COMPARE registers and the interruption are not implemented.
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| /qemu/docs/system/arm/ |
| H A D | collie.rst | 7 Implemented devices:
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| /qemu/hw/s390x/ |
| H A D | s390-hypercall.h | 17 #define DIAG500_VIRTIO_NOTIFY 0 /* legacy, implemented as a NOP */
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| /qemu/hw/display/ |
| H A D | sm501.c | 806 "sm501: rop%d op %x%s not implemented\n", in sm501_2d_operation()
926 qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n", in sm501_2d_operation()
994 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" in sm501_system_config_read()
1049 " implemented.\n"); in sm501_system_config_write()
1054 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" in sm501_system_config_write()
1089 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." in sm501_i2c_read()
1147 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. " in sm501_i2c_write()
1209 /* Not implemented yet */ in sm501_disp_ctrl_read()
1300 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " in sm501_disp_ctrl_read()
1321 /* Not implemented yet */ in sm501_disp_ctrl_write()
[all …]
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