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/linux-6.8/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
/linux-6.8/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
[all …]
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.8/arch/powerpc/boot/dts/
Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
[all …]
/linux-6.8/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.8/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
26 * Utility Routine to erase a J-TLB entry
63 /* Locate the TLB entry for this vaddr + ASID */ in tlb_entry_erase()
82 * This also sets up PD0 (vaddr, ASID..) for final commit in tlb_entry_insert()
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
95 /* setup the other half of TLB entry (pfn, rwx..) */ in tlb_entry_insert()
101 * which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert()
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/linux-6.8/arch/powerpc/kernel/
Dsetup_64.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 #include <asm/asm-prototypes.h>
63 #include <asm/code-patching.h>
68 #include <asm/feature-fixups.h>
101 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
103 * set up this TLB. in setup_tlb_core_data()
108 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
112 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
127 /* Look for ibm,smt-enabled OF option */
154 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
[all …]
/linux-6.8/arch/powerpc/include/asm/nohash/32/
Dpte-44x.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
43 * into TLB entry.
45 * - PRESENT *must* be in the bottom three bits because swap cache
[all …]
Dpte-85xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
14 - PRESENT *must* be in the bottom two bits because swap PTEs use
19 /* Definitions for FSL Book-E Cores */
30 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */
47 * We define 2 sets of base prot bits, one for basic pages (ie,
59 #include <asm/pgtable-masks.h>
/linux-6.8/include/asm-generic/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
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/linux-6.8/arch/mips/kvm/
Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
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/linux-6.8/arch/parisc/include/asm/
Dropes.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
30 void __iomem *ioc_hpa; /* I/O MMU base address */
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
99 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
103 return d->id.hversion == IKE_MERCED_PORT; in IS_IKE()
[all …]
/linux-6.8/arch/powerpc/mm/
Dinit_32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
37 #include <asm/tlb.h>
47 /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */
48 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET))
77 * MMU_init sets up the basic memory mappings for the kernel,
78 * including both RAM and possibly some I/O regions,
79 * and sets up the page tables and the MMU hardware ready to go.
86 total_lowmem = total_memory = memblock_end_of_DRAM() - memstart_addr; in MMU_init()
[all …]
/linux-6.8/arch/openrisc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
48 int i; in local_flush_tlb_all() local
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
[all …]
/linux-6.8/arch/powerpc/mm/book3s64/
Dradix_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TLB flush routines for radix kernels.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
15 #include <asm/ppc-opcode.h>
16 #include <asm/tlb.h>
26 * i.e., r=1 and is=01 or is=10 or is=11
39 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
50 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
51 * and partition table entries. Then flush the remaining sets of the in tlbiel_all_isa300()
52 * TLB. in tlbiel_all_isa300()
[all …]
/linux-6.8/arch/arm/mm/
Dproc-arm720.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
8 * hacked for non-paged-MM by Hyok S. Choi, 2004.
10 * These are the low level assembler for performing cache and TLB
15 * 05-09-2000 SJH Created by moving 720 specific functions
16 * out of 'proc-arm6,7.S' per RMK discussion
17 * 07-25-2000 SJH Added idle function.
18 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
19 * 04-20-2004 HSC modified for non-paged memory management mode.
25 #include <asm/asm-offsets.h>
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/linux-6.8/arch/powerpc/kvm/
De500_mmu_host.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved.
30 #include <asm/pte-walk.h>
38 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1)
45 return host_tlb_params[1].entries - tlbcam_index - 1; in tlb1_max_shadow_size()
67 * writing shadow tlb entry to host TLB
77 mtspr(SPRN_MAS1, stlbe->mas1); in __write_host_tlbe()
78 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); in __write_host_tlbe()
79 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); in __write_host_tlbe()
80 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); in __write_host_tlbe()
[all …]
/linux-6.8/arch/x86/mm/
Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
23 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
25 tlb_remove_page(tlb, table); in paravirt_tlb_remove_table()
39 return -EINVAL; in setup_userpte()
48 return -EINVAL; in setup_userpte()
53 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
57 paravirt_tlb_remove_table(tlb, pte); in ___pte_free_tlb()
61 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
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/linux-6.8/Documentation/arch/x86/x86_64/
Dboot-options.rst1 .. SPDX-License-Identifier: GPL-2.0
22 due to the shared banks, i.e. you might get duplicated
39 Do not opt-in to Local MCE delivery. Use legacy method
52 Sets the time in us to wait for other CPUs on machine checks. 0
55 Don't overwrite the bios-set CMCI threshold. This boot option
57 bios. Without this option, Linux always sets the CMCI
59 analysis less effective if the bios sets thresholds for memory
62 Force-enable recoverable machine check code paths
73 Use IO-APIC. Default
76 Don't use the IO-APIC.
[all …]
/linux-6.8/drivers/parisc/
Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
9 ** (c) Copyright 2000 Hewlett-Packard Company
13 ** the I/O MMU - basically what x86 does.
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
19 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
20 ** the coherency design originally worked out. Only PCX-W does.
[all …]
/linux-6.8/arch/powerpc/include/asm/book3s/64/
Dmmu-hash.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-const.h>
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
128 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
129 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
130 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
131 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
192 return -1; in shift_to_mmu_psize()
211 return -1; in ap_to_shift()
249 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) argument
[all …]
/linux-6.8/Documentation/arch/x86/
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
62 to perform I/O operations via use of PASID.
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
[all …]
/linux-6.8/arch/mips/mm/
Dc-octeon.c6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
33 * Octeon automatically flushes the dcache on tlb changes, so
49 * Flush local I-cache for the specified range.
58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores
82 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
109 * octeon_flush_cache_mm - flush all memory associated with a memory context.
133 * octeon_flush_cache_range - Flush a range out of a vma
142 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
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