Lines Matching +full:i +full:- +full:tlb +full:- +full:sets

1 /* SPDX-License-Identifier: GPL-2.0 */
9  * Because of the 3 word TLB entries to support 36-bit addressing,
11  * are easily loaded during exception processing.  I decided to
16  * ERPN fields in the TLB. -Matt
19  * easier to move into the TLB from the PTE. -BenH.
25  * PPC 440 core has following TLB attribute fields;
29  *   RPN.................................  -  -  -  -  -  - ERPN.......
33  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
43  * into TLB entry.
45  *   - PRESENT *must* be in the bottom three bits because swap cache
48  *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
50  *     have -some- form of SMP support and so I keep the bit there for
53  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
55  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
60  * PTE. In case of a swap PTE, LSB 2-24 are used to store information regarding
61  * the swap entry. However LSB 0-1 still hold protection values, for example,
75 #define _PAGE_NO_CACHE	0x00000400		/* H: I bit */
91  * We define 2 sets of base prot bits, one for basic pages (ie,
103 #include <asm/pgtable-masks.h>