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/linux-5.10/arch/arm/boot/dts/
Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/pinctrl/samsung.h>
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
24 interrupt-controller;
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Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 Hisilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
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Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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/linux-5.10/Documentation/devicetree/bindings/gpio/
Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
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D8xxx_gpio.txt1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
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Dgpio-mxs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MXS GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
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Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
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Dbrcm,brcmstb-gpio.txt1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
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Dintel,ixp4xx-gpio.txt1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
4 It supports 16 GPIO lines.
6 The interrupt portions of the GPIO controller is hierarchical:
7 the synchronous edge detector is part of the GPIO block, but the
9 main IXP4xx interrupt controller which has a 1:1 mapping for
10 the first 12 GPIO lines to 12 system interrupts.
12 The remaining 4 GPIO lines can not be used for receiving
15 The interrupt parent of this GPIO controller must be the
16 IXP4xx interrupt controller.
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Dsnps,dw-apb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as desribed in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
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Dgpio-eic-sprd.txt1 Spreadtrum EIC controller bindings
3 The EIC is the abbreviation of external interrupt controller, which can
6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
7 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
10 The EIC-debounce sub-module provides up to 8 source input signal
12 stable status (millisecond resolution) and a single-trigger mechanism
13 is introduced into this sub-module to enhance the input event detection
14 reliability. In addition, this sub-module's clock can be shut off
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
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Dgpio-atlas7.txt1 CSR SiRFatlas7 GPIO controller bindings
4 - compatible : "sirf,atlas7-gpio"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-banks : How many gpio banks on this controller
8 - gpio-controller : Indicates this device is a GPIO controller
9 - interrupt-controller : Marks the device node as an interrupt controller
11 The GPIO controller also acts as an interrupt controller. It uses the default
13 interrupt-controller/interrupts.txt.
18 compatible = "sirf,atlas7-gpio";
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Dgpio-davinci.txt1 Davinci/Keystone GPIO controller bindings
4 - compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
5 "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
7 "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
8 "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
9 "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs
11 - reg: Physical base address of the controller and the size of memory mapped
14 - gpio-controller : Marks the device node as a gpio controller.
16 - #gpio-cells : Should be two.
17 - first cell is the pin number
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Dnxp,lpc1850-gpio.txt1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
2 -----------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
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/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
33 gpio-controller;
[all …]
Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
24 gpio-controller;
25 #gpio-cells = <2>;
27 interrupt-controller;
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/linux-5.10/arch/powerpc/boot/dts/
Dmucmc52.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
12 /* Timer pins that need to be in GPIO mode */
13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
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/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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/linux-5.10/arch/arc/boot/dts/
Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
/linux-5.10/arch/mips/boot/dts/pic32/
Dpic32mzda.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/microchip,pic32-clock.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&evic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
43 compatible = "microchip,pic32mzda-infra";
49 #clock-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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