Lines Matching +full:gpio +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53";
69 enable-method = "psci";
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
80 compatible = "arm,cortex-a53";
83 enable-method = "psci";
87 compatible = "arm,cortex-a73";
90 enable-method = "psci";
94 compatible = "arm,cortex-a73";
97 enable-method = "psci";
101 compatible = "arm,cortex-a73";
104 enable-method = "psci";
108 compatible = "arm,cortex-a73";
111 enable-method = "psci";
115 gic: interrupt-controller@e82b0000 {
116 compatible = "arm,gic-400";
121 #interrupt-cells = <3>;
122 #address-cells = <0>;
125 interrupt-controller;
129 compatible = "arm,armv8-timer";
130 interrupt-parent = <&gic>;
139 clock-frequency = <1920000>;
143 compatible = "simple-bus";
144 #address-cells = <2>;
145 #size-cells = <2>;
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
151 #clock-cells = <1>;
155 compatible = "hisilicon,hi3670-reset",
156 "hisilicon,hi3660-reset";
157 #reset-cells = <2>;
158 hisi,rst-syscon = <&crg_ctrl>;
162 compatible = "hisilicon,hi3670-pctrl", "syscon";
164 #clock-cells = <1>;
168 compatible = "hisilicon,hi3670-pmuctrl", "syscon";
170 #clock-cells = <1>;
174 compatible = "hisilicon,hi3670-sctrl", "syscon";
176 #clock-cells = <1>;
180 compatible = "hisilicon,hi3670-iomcu", "syscon";
182 #clock-cells = <1>;
186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
188 #clock-cells = <1>;
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
194 #clock-cells = <1>;
203 clock-names = "uartclk", "apb_pclk";
204 pinctrl-names = "default";
205 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
215 clock-names = "uartclk", "apb_pclk";
216 pinctrl-names = "default";
226 clock-names = "uartclk", "apb_pclk";
227 pinctrl-names = "default";
228 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
238 clock-names = "uartclk", "apb_pclk";
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
250 clock-names = "uartclk", "apb_pclk";
251 pinctrl-names = "default";
252 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
262 clock-names = "uartclk", "apb_pclk";
263 pinctrl-names = "default";
273 clock-names = "uartclk", "apb_pclk";
274 pinctrl-names = "default";
275 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
279 gpio0: gpio@e8a0b000 {
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
289 clock-names = "apb_pclk";
292 gpio1: gpio@e8a0c000 {
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
301 clock-names = "apb_pclk";
304 gpio2: gpio@e8a0d000 {
308 gpio-controller;
309 #gpio-cells = <2>;
310 gpio-ranges = <&pmx0 1 6 7>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
314 clock-names = "apb_pclk";
317 gpio3: gpio@e8a0e000 {
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
327 clock-names = "apb_pclk";
330 gpio4: gpio@e8a0f000 {
334 gpio-controller;
335 #gpio-cells = <2>;
336 gpio-ranges = <&pmx0 0 18 8>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
340 clock-names = "apb_pclk";
343 gpio5: gpio@e8a10000 {
347 gpio-controller;
348 #gpio-cells = <2>;
349 gpio-ranges = <&pmx0 0 26 8>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
353 clock-names = "apb_pclk";
356 gpio6: gpio@e8a11000 {
360 gpio-controller;
361 #gpio-cells = <2>;
362 gpio-ranges = <&pmx0 1 34 7>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
366 clock-names = "apb_pclk";
369 gpio7: gpio@e8a12000 {
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pmx0 0 41 8>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
379 clock-names = "apb_pclk";
382 gpio8: gpio@e8a13000 {
386 gpio-controller;
387 #gpio-cells = <2>;
388 gpio-ranges = <&pmx0 0 49 8>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
392 clock-names = "apb_pclk";
395 gpio9: gpio@e8a14000 {
399 gpio-controller;
400 #gpio-cells = <2>;
401 gpio-ranges = <&pmx0 0 57 8>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
405 clock-names = "apb_pclk";
408 gpio10: gpio@e8a15000 {
412 gpio-controller;
413 #gpio-cells = <2>;
414 gpio-ranges = <&pmx0 0 65 8>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
418 clock-names = "apb_pclk";
421 gpio11: gpio@e8a16000 {
425 gpio-controller;
426 #gpio-cells = <2>;
427 gpio-ranges = <&pmx0 0 73 8>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
431 clock-names = "apb_pclk";
434 gpio12: gpio@e8a17000 {
438 gpio-controller;
439 #gpio-cells = <2>;
440 gpio-ranges = <&pmx0 0 81 1>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
444 clock-names = "apb_pclk";
447 gpio13: gpio@e8a18000 {
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
456 clock-names = "apb_pclk";
459 gpio14: gpio@e8a19000 {
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
468 clock-names = "apb_pclk";
471 gpio15: gpio@e8a1a000 {
475 gpio-controller;
476 #gpio-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
480 clock-names = "apb_pclk";
483 gpio16: gpio@e8a1b000 {
487 gpio-controller;
488 #gpio-cells = <2>;
489 gpio-ranges = <&pmx5 0 0 8>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
493 clock-names = "apb_pclk";
496 gpio17: gpio@e8a1c000 {
500 gpio-controller;
501 #gpio-cells = <2>;
502 gpio-ranges = <&pmx5 0 8 2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
506 clock-names = "apb_pclk";
509 gpio18: gpio@fff28000 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 gpio-ranges = <&pmx1 4 42 4>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
519 clock-names = "apb_pclk";
522 gpio19: gpio@fff29000 {
526 gpio-controller;
527 #gpio-cells = <2>;
528 gpio-ranges = <&pmx1 0 61 2>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
532 clock-names = "apb_pclk";
535 gpio20: gpio@e8a1f000 {
539 gpio-controller;
540 #gpio-cells = <2>;
541 gpio-ranges = <&pmx7 0 0 8>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
545 clock-names = "apb_pclk";
548 gpio21: gpio@e8a20000 {
552 gpio-controller;
553 #gpio-cells = <2>;
554 gpio-ranges = <&pmx7 0 8 4>;
555 interrupt-controller;
556 #interrupt-cells = <2>;
558 clock-names = "apb_pclk";
561 gpio22: gpio@fff0b000 {
565 gpio-controller;
566 #gpio-cells = <2>;
568 gpio-ranges = <&pmx1 2 0 6>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
572 clock-names = "apb_pclk";
575 gpio23: gpio@fff0c000 {
579 gpio-controller;
580 #gpio-cells = <2>;
582 gpio-ranges = <&pmx1 0 6 8>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
586 clock-names = "apb_pclk";
589 gpio24: gpio@fff0d000 {
593 gpio-controller;
594 #gpio-cells = <2>;
596 gpio-ranges = <&pmx1 0 14 8>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
600 clock-names = "apb_pclk";
603 gpio25: gpio@fff0e000 {
607 gpio-controller;
608 #gpio-cells = <2>;
610 gpio-ranges = <&pmx1 0 22 8>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
614 clock-names = "apb_pclk";
617 gpio26: gpio@fff0f000 {
621 gpio-controller;
622 #gpio-cells = <2>;
624 gpio-ranges = <&pmx1 0 30 1>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
628 clock-names = "apb_pclk";
631 gpio27: gpio@fff10000 {
635 gpio-controller;
636 #gpio-cells = <2>;
638 gpio-ranges = <&pmx1 4 31 4>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
642 clock-names = "apb_pclk";
645 gpio28: gpio@fff1d000 {
649 gpio-controller;
650 #gpio-cells = <2>;
651 gpio-ranges = <&pmx1 1 35 7>;
652 interrupt-controller;
653 #interrupt-cells = <2>;
655 clock-names = "apb_pclk";
660 compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
665 interrupt-parent = <&gic>;
669 clock-names = "ref_clk", "phy_clk";
670 freq-table-hz = <0 0>, <0 0>;
673 reset-names = "rst";
678 compatible = "hisilicon,hi3670-dw-mshc",
679 "hisilicon,hi3660-dw-mshc";
681 #address-cells = <1>;
682 #size-cells = <0>;
686 clock-names = "ciu", "biu";
687 clock-frequency = <3200000>;
689 reset-names = "reset";
690 hisilicon,peripheral-syscon = <&sctrl>;
691 card-detect-delay = <200>;
697 compatible = "hisilicon,hi3670-dw-mshc",
698 "hisilicon,hi3660-dw-mshc";
700 #address-cells = <1>;
701 #size-cells = <0>;
705 clock-names = "ciu", "biu";
706 clock-frequency = <3200000>;
708 reset-names = "reset";
709 card-detect-delay = <200>;