Home
last modified time | relevance | path

Searched full:gem (Results 1 – 19 of 19) sorted by relevance

/qemu/include/hw/net/
H A Dcadence_gem.h2 * QEMU Cadence GEM emulation
35 #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
66 /* GEM registers backing store */
/qemu/hw/misc/
H A Dxlnx-versal-crl.c128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); in crl_rst_gem1_prew()
368 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { in crl_init()
369 object_property_add_link(obj, "gem[*]", TYPE_DEVICE, in crl_init()
370 (Object **)&s->cfg.gem[i], in crl_init()
376 (Object **)&s->cfg.gem[i], in crl_init()
/qemu/hw/arm/
H A Dxlnx-zynqmp.c394 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); in xlnx_zynqmp_init()
395 object_initialize_child(obj, "gem-irq-orgate[*]", in xlnx_zynqmp_init()
621 qemu_configure_nic_device(DEVICE(&s->gem[i]), true, NULL); in xlnx_zynqmp_realize()
622 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, in xlnx_zynqmp_realize()
624 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, in xlnx_zynqmp_realize()
626 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, in xlnx_zynqmp_realize()
633 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { in xlnx_zynqmp_realize()
636 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); in xlnx_zynqmp_realize()
637 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, in xlnx_zynqmp_realize()
639 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 1, in xlnx_zynqmp_realize()
H A Dxlnx-versal.c253 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { in versal_create_gems()
256 char *name = g_strdup_printf("gem%d", i); in versal_create_gems()
261 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], in versal_create_gems()
264 object_initialize_child(OBJECT(s), "gem-irq-orgate[*]", in versal_create_gems()
266 dev = DEVICE(&s->lpd.iou.gem[i]); in versal_create_gems()
767 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { in versal_create_crl()
768 g_autofree gchar *name = g_strdup_printf("gem[%d]", i); in versal_create_crl()
771 name, OBJECT(&s->lpd.iou.gem[i]), in versal_create_crl()
H A Dxlnx-versal-virt.c293 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; in fdt_add_gem_nodes()
/qemu/hw/riscv/
H A Dsifive_u.c16 * 6) GEM (Gigabit Ethernet Controller) and management block
405 "sifive,fu540-c000-gem"); in create_fdt()
421 s->soc.gem.conf.macaddr.a, ETH_ALEN); in create_fdt()
775 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); in type_init()
897 qemu_configure_nic_device(DEVICE(&s->gem), true, NULL); in sifive_u_soc_realize()
898 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, in sifive_u_soc_realize()
900 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { in sifive_u_soc_realize()
903 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); in sifive_u_soc_realize()
904 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, in sifive_u_soc_realize()
923 create_unimplemented_device("riscv.sifive.u.gem-mgmt", in sifive_u_soc_realize()
H A Dmicrochip_pfsoc.c17 * 6) GEM (Gigabit Ethernet MAC Controller)
65 /* GEM version */
/qemu/hw/mem/
H A Dcxl_type3.c1636 CXLEventGenMedia gem; in qmp_cxl_inject_general_media_event() local
1637 CXLEventRecordHdr *hdr = &gem.hdr; in qmp_cxl_inject_general_media_event()
1662 memset(&gem, 0, sizeof(gem)); in qmp_cxl_inject_general_media_event()
1663 cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem), in qmp_cxl_inject_general_media_event()
1666 stq_le_p(&gem.phys_addr, dpa); in qmp_cxl_inject_general_media_event()
1667 gem.descriptor = descriptor; in qmp_cxl_inject_general_media_event()
1668 gem.type = type; in qmp_cxl_inject_general_media_event()
1669 gem.transaction_type = transaction_type; in qmp_cxl_inject_general_media_event()
1672 gem.channel = channel; in qmp_cxl_inject_general_media_event()
1677 gem.rank = rank; in qmp_cxl_inject_general_media_event()
[all …]
/qemu/tests/functional/
H A Dtest_ppc64_mac99.py38 self.wait_for_console_pattern('gem 0000:f0:0e.0 eth0: Link is up at 100 Mbps')
/qemu/docs/system/riscv/
H A Dsifive_u.rst20 * 1 GEM Ethernet controller
77 it to generate a unique MAC address to be programmed to the on-chip GEM
204 …-append "gem(0,0)host:vxWorks h=192.168.200.1 e=192.168.200.2:ffffff00 u=target pw=vxTarget f=0x01"
H A Dmicrochip-icicle-kit.rst26 * 2 GEM Ethernet controllers
/qemu/include/hw/riscv/
H A Dsifive_u.h54 CadenceGEMState gem; member
/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h631 * outside of the GEM object in a reserved memory area dedicated for the
632 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
643 * GEM object in a reserved memory area dedicated for the storage of the
644 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
653 * outside of the GEM object in a reserved memory area dedicated for the
654 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
713 * GEM object in a reserved memory area dedicated for the storage of the
714 * CCS data for all compressible GEM objects.
725 * GEM object in a reserved memory area dedicated for the storage of the
726 * CCS data for all compressible GEM objects. The GEM object must be stored in
/qemu/include/hw/arm/
H A Dxlnx-zynqmp.h118 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; member
H A Dxlnx-versal.h80 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; member
/qemu/include/hw/misc/
H A Dxlnx-versal-crl.h227 DeviceState *gem[2]; member
/qemu/hw/net/
H A Dcadence_gem.c2 * QEMU Cadence GEM emulation
771 * Calculate a GEM MAC Address hash index
1574 * Read a GEM register.
1607 * Write a GEM register.
H A Dsungem.c2 * QEMU model of SUN GEM ethernet controller
620 /* Note: The real GEM will fetch descriptors in blocks of 4, in sungem_receive()
/qemu/hw/ppc/
H A Dmac_newworld.c45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]