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Searched +full:fan +full:- +full:controller (Results 1 – 7 of 7) sorted by relevance

/qemu/hw/sensor/
H A Dmax31785.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Maxim MAX31785 PMBus 6-Channel Fan Controller
80 /* fan speed in RPM */
92 * | 0 | Fan Connected to PWM0 |
94 * | 1 | Fan Connected to PWM1 |
96 * | 2 | Fan Connected to PWM2 |
98 * | 3 | Fan Connected to PWM3 |
100 * | 4 | Fan Connected to PWM4 |
102 * | 5 | Fan Connected to PWM5 |
140 * |23-254 | Reserved |
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/qemu/docs/system/arm/
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz).
15 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
16 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
17 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
22 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
23 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
24 - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
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/qemu/hw/misc/
H A Dnpcm7xx_mft.c19 #include "hw/qdev-clock.h"
20 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
36 * Some of the registers can only accessed via 16-bit ops and some can only
37 * be accessed via 8-bit ops. However we mark all of them using REG16 to
101 /* Each fan revolution should generated 2 pulses */
119 s->regs[i] = 0; in npcm7xx_mft_reset()
127 * Both iclr and ictrl are 8-bit regs. (See npcm7xx_mft_check_mem_op) in npcm7xx_mft_clear_interrupt()
129 s->regs[R_NPCM7XX_MFT_ICTRL] &= ~iclr; in npcm7xx_mft_clear_interrupt()
136 * Otherwise return -1.
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/qemu/hw/arm/
H A Dstm32l4x5_soc.c4 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
27 #include "system/address-spaces.h"
29 #include "hw/or-irq.h"
33 #include "hw/qdev-clock.h"
49 * Some IRQs are connected to the same CPU IRQ (denoted by -1)
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H A Daspeed.c9 * the COPYING file in the top-level directory.
25 #include "hw/qdev-properties.h"
26 #include "system/block-backend.h"
29 #include "qemu/error-report.h"
32 #include "hw/qdev-clock.h"
36 .board_id = -1, /* device-tree-only board */
53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
166 /* Quanta-Q71l hardware value */
204 /* Qualcomm DC-SCM hardware value */
222 * r2 = per-cpu go sign value in aspeed_write_smpboot()
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/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py24 # SPDX-License-Identifier: BSD-3-Clause
45 if sys.platform == "BITS-EFI":
92 print "Failure: Type {} - not found".format(num)
140 self.strings_length = u.offset - self.strings_offset
167 return self.strings[i - 1]
186 characteristic_bytes = self.length - 0x12
319 0x0F: 'Space-saving',
328 0x18: 'Sealed-case PC',
329 0x19: 'Multi-system chassis W',
347 0x06: 'Non-recoverable',
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/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
75 F: docs/devel/build-environment.rst
76 F: docs/devel/code-of-conduct.rst
78 F: docs/devel/conflict-resolution.rst
80 F: docs/devel/submitting-a-patch.rst
81 F: docs/devel/submitting-a-pull-request.rst
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