Lines Matching +full:fan +full:- +full:controller
19 #include "hw/qdev-clock.h"
20 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
36 * Some of the registers can only accessed via 16-bit ops and some can only
37 * be accessed via 8-bit ops. However we mark all of them using REG16 to
101 /* Each fan revolution should generated 2 pulses */
119 s->regs[i] = 0; in npcm7xx_mft_reset()
127 * Both iclr and ictrl are 8-bit regs. (See npcm7xx_mft_check_mem_op) in npcm7xx_mft_clear_interrupt()
129 s->regs[R_NPCM7XX_MFT_ICTRL] &= ~iclr; in npcm7xx_mft_clear_interrupt()
136 * Otherwise return -1.
148 return tgt - 1; in npcm7xx_mft_compare()
151 return -1; in npcm7xx_mft_compare()
154 /* Compute CNT according to corresponding fan's RPM. */
181 count = -1; in npcm7xx_mft_compute_cnt()
184 count = NPCM7XX_MFT_MAX_CNT - count; in npcm7xx_mft_compute_cnt()
187 if (stopped == -1) { in npcm7xx_mft_compute_cnt()
188 if (count == -1) { in npcm7xx_mft_compute_cnt()
199 if (count != -1) { in npcm7xx_mft_compute_cnt()
202 trace_npcm7xx_mft_rpm(clock->canonical_path, clock_get_hz(clock), in npcm7xx_mft_compute_cnt()
208 * Capture Fan RPM and update CNT and CR registers accordingly.
222 if (!(s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_MODE5)) { in npcm7xx_mft_capture()
227 if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TAEN && in npcm7xx_mft_capture()
228 s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) { in npcm7xx_mft_capture()
229 sel = s->regs[R_NPCM7XX_MFT_INASEL] & NPCM7XX_MFT_INASEL_SELA; in npcm7xx_mft_capture()
230 cpcfg = NPCM7XX_MFT_CPCFG_GET_A(s->regs[R_NPCM7XX_MFT_CPCFG]); in npcm7xx_mft_capture()
231 state = npcm7xx_mft_compute_cnt(s->clock_1, in npcm7xx_mft_capture()
232 sel ? s->max_rpm[2] : s->max_rpm[0], in npcm7xx_mft_capture()
233 sel ? s->duty[2] : s->duty[0], in npcm7xx_mft_capture()
234 s->regs[R_NPCM7XX_MFT_CPA], in npcm7xx_mft_capture()
236 &s->regs[R_NPCM7XX_MFT_CNT1]); in npcm7xx_mft_capture()
239 /* Interrupt on input capture on TAn transition - TAPND */ in npcm7xx_mft_capture()
240 s->regs[R_NPCM7XX_MFT_CRA] = s->regs[R_NPCM7XX_MFT_CNT1]; in npcm7xx_mft_capture()
241 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TAPND; in npcm7xx_mft_capture()
242 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TAIEN) { in npcm7xx_mft_capture()
248 /* Compare Hit - TEPND */ in npcm7xx_mft_capture()
249 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TEPND; in npcm7xx_mft_capture()
250 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TEIEN) { in npcm7xx_mft_capture()
256 /* Underflow - TCPND */ in npcm7xx_mft_capture()
257 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TCPND; in npcm7xx_mft_capture()
258 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TCIEN) { in npcm7xx_mft_capture()
269 if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TBEN && in npcm7xx_mft_capture()
270 s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) { in npcm7xx_mft_capture()
271 sel = s->regs[R_NPCM7XX_MFT_INBSEL] & NPCM7XX_MFT_INBSEL_SELB; in npcm7xx_mft_capture()
272 cpcfg = NPCM7XX_MFT_CPCFG_GET_B(s->regs[R_NPCM7XX_MFT_CPCFG]); in npcm7xx_mft_capture()
273 state = npcm7xx_mft_compute_cnt(s->clock_2, in npcm7xx_mft_capture()
274 sel ? s->max_rpm[3] : s->max_rpm[1], in npcm7xx_mft_capture()
275 sel ? s->duty[3] : s->duty[1], in npcm7xx_mft_capture()
276 s->regs[R_NPCM7XX_MFT_CPB], in npcm7xx_mft_capture()
278 &s->regs[R_NPCM7XX_MFT_CNT2]); in npcm7xx_mft_capture()
281 /* Interrupt on input capture on TBn transition - TBPND */ in npcm7xx_mft_capture()
282 s->regs[R_NPCM7XX_MFT_CRB] = s->regs[R_NPCM7XX_MFT_CNT2]; in npcm7xx_mft_capture()
283 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TBPND; in npcm7xx_mft_capture()
284 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TBIEN) { in npcm7xx_mft_capture()
290 /* Compare Hit - TFPND */ in npcm7xx_mft_capture()
291 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TFPND; in npcm7xx_mft_capture()
292 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TFIEN) { in npcm7xx_mft_capture()
298 /* Underflow - TDPND */ in npcm7xx_mft_capture()
299 s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TDPND; in npcm7xx_mft_capture()
300 if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TDIEN) { in npcm7xx_mft_capture()
310 trace_npcm7xx_mft_capture(DEVICE(s)->canonical_path, irq_level); in npcm7xx_mft_capture()
311 qemu_set_irq(s->irq, irq_level); in npcm7xx_mft_capture()
320 prescaled_clock_period = clock_get(s->clock_in) * in npcm7xx_mft_update_clock()
321 (s->regs[R_NPCM7XX_MFT_PRSC] + 1ULL); in npcm7xx_mft_update_clock()
322 trace_npcm7xx_mft_update_clock(s->clock_in->canonical_path, in npcm7xx_mft_update_clock()
323 s->regs[R_NPCM7XX_MFT_CKC], in npcm7xx_mft_update_clock()
324 clock_get(s->clock_in), in npcm7xx_mft_update_clock()
327 if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) { in npcm7xx_mft_update_clock()
329 clock_update(s->clock_1, prescaled_clock_period); in npcm7xx_mft_update_clock()
332 clock_update(s->clock_1, 0); in npcm7xx_mft_update_clock()
335 if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) { in npcm7xx_mft_update_clock()
337 clock_update(s->clock_2, prescaled_clock_period); in npcm7xx_mft_update_clock()
340 clock_update(s->clock_2, 0); in npcm7xx_mft_update_clock()
354 "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n", in npcm7xx_mft_read()
359 value = s->regs[offset / 2]; in npcm7xx_mft_read()
362 trace_npcm7xx_mft_read(DEVICE(s)->canonical_path, offset, value); in npcm7xx_mft_read()
371 trace_npcm7xx_mft_write(DEVICE(s)->canonical_path, offset, v); in npcm7xx_mft_write()
379 s->regs[offset / 2] = v; in npcm7xx_mft_write()
384 s->regs[offset / 2] = v; in npcm7xx_mft_write()
395 /* 16-bit registers. Must be accessed with 16-bit read/write.*/ in npcm7xx_mft_check_mem_op()
404 /* 8-bit registers. Must be accessed with 8-bit read/write.*/ in npcm7xx_mft_check_mem_op()
447 trace_npcm7xx_mft_set_duty(DEVICE(s)->canonical_path, n, value); in npcm7xx_mft_duty_handler()
448 s->duty[n] = value; in npcm7xx_mft_duty_handler()
475 qemu_irq_lower(s->irq); in npcm7xx_mft_hold_reset()
484 memory_region_init_io(&s->iomem, obj, &npcm7xx_mft_ops, s, in npcm7xx_mft_init()
486 sysbus_init_mmio(sbd, &s->iomem); in npcm7xx_mft_init()
487 sysbus_init_irq(sbd, &s->irq); in npcm7xx_mft_init()
488 s->clock_in = qdev_init_clock_in(dev, "clock-in", npcm7xx_mft_update_clock, in npcm7xx_mft_init()
490 s->clock_1 = qdev_init_clock_out(dev, "clock1"); in npcm7xx_mft_init()
491 s->clock_2 = qdev_init_clock_out(dev, "clock2"); in npcm7xx_mft_init()
497 NULL, &s->max_rpm[i]); in npcm7xx_mft_init()
504 .name = "npcm7xx-mft-module",
523 dc->desc = "NPCM7xx MFT Controller"; in npcm7xx_mft_class_init()
524 dc->vmsd = &vmstate_npcm7xx_mft; in npcm7xx_mft_class_init()
525 rc->phases.enter = npcm7xx_mft_enter_reset; in npcm7xx_mft_class_init()
526 rc->phases.hold = npcm7xx_mft_hold_reset; in npcm7xx_mft_class_init()