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/qemu/include/hw/nvram/
H A Dxlnx-efuse.h2 * QEMU model of the Xilinx eFuse core
33 #define TYPE_XLNX_EFUSE "xlnx-efuse"
69 * @s: the efuse object
70 * @bit: the efuse bit-address to read the data
78 * @s: the efuse object
79 * @bit: the efuse bit-address to be written a value of 1
87 * @s: the efuse object
89 * @start: the efuse bit-address (which must be multiple of 32) of the
101 * @s: the efuse object
103 * This function inspects a number of efuse bits at specific addresses
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H A Dxlnx-versal-efuse.h28 #include "hw/nvram/xlnx-efuse.h"
32 #define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx-versal-efuse"
33 #define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx-pmc-efuse-cache"
42 XlnxEFuse *efuse; member
56 XlnxEFuse *efuse; member
61 * @s: the efuse object
H A Dxlnx-zynqmp-efuse.h28 #include "hw/nvram/xlnx-efuse.h"
32 #define TYPE_XLNX_ZYNQMP_EFUSE "xlnx-zynqmp-efuse"
39 XlnxEFuse *efuse; member
/qemu/hw/nvram/
H A Dmeson.build11 system_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
12 system_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
14 'xlnx-versal-efuse-cache.c',
15 'xlnx-versal-efuse-ctrl.c'))
17 'xlnx-zynqmp-efuse.c'))
H A Dxlnx-versal-efuse-ctrl.c2 * QEMU model of the Versal eFuse controller
27 #include "hw/nvram/xlnx-versal-efuse.h"
160 * eFuse layout references:
261 uint32_t check = xlnx_efuse_tbits_check(s->efuse); in efuse_status_tbits_sync()
275 if (!s->efuse || !s->efuse->init_tbits) { in efuse_anchor_bits_check()
279 for (page = 0; page < s->efuse->efuse_nr; page++) { in efuse_anchor_bits_check()
286 if (!xlnx_efuse_get_bit(s->efuse, bit)) { in efuse_anchor_bits_check()
287 xlnx_efuse_set_bit(s->efuse, bit); in efuse_anchor_bits_check()
291 if (!xlnx_efuse_get_bit(s->efuse, bit)) { in efuse_anchor_bits_check()
292 xlnx_efuse_set_bit(s->efuse, bit); in efuse_anchor_bits_check()
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H A Dxlnx-zynqmp-efuse.c2 * QEMU model of the ZynqMP eFuse
29 #include "hw/nvram/xlnx-zynqmp-efuse.h"
56 FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
60 FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
202 * eFUSE layout references:
261 (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
265 ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
274 unsigned int check = xlnx_efuse_tbits_check(s->efuse); in update_tbit_status()
284 /* Update the u32 array from efuse bits. Slow but simple approach. */
304 u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits; in cache_sync_u32()
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H A Dxlnx-efuse.c2 * QEMU model of the EFUSE eFuse
28 #include "hw/nvram/xlnx-efuse.h"
76 warn_report("%s: Skip saving updates to read-only eFUSE backstore.", in efuse_bdrv_read()
81 error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.", in efuse_bdrv_read()
109 error_report("%s: Failed to write offset %u of eFUSE backstore.", in efuse_bdrv_sync()
152 "Ignored setting of readonly efuse bit<%u,%u>!\n", in xlnx_efuse_set_bit()
216 "%s.efuse-size: %u: property value not multiple of 32.", in efuse_realize()
261 .description = "Node name or ID of a block device to use as eFUSE backend",
270 DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
271 DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
H A Dxlnx-versal-efuse-cache.c26 #include "hw/nvram/xlnx-versal-efuse.h"
43 ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL); in efuse_cache_read()
46 ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL); in efuse_cache_read()
62 qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only", in efuse_cache_write()
87 DEFINE_PROP_LINK("efuse",
88 XlnxVersalEFuseCache, efuse,
H A Dxlnx-efuse-crc.c2 * Xilinx eFuse/bbram CRC calculator
25 #include "hw/nvram/xlnx-efuse.h"
67 * eFuse calculation is shown here: in xlnx_efuse_u37_crc()
H A Dxlnx-bbram.c36 #include "hw/nvram/xlnx-efuse.h"
/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst36 - eFUSE (3072 bytes of one-time field-programmable bit array)
202 eFUSE File Backend
204 eFUSE can have an optional file backend, which must be a seekable
208 To add a file-backend for the eFUSE:
212 -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
218 -global xlnx-efuse.drive-index=N
221 In actual physical Versal, BBRAM and eFUSE contain sensitive data.
/qemu/include/hw/arm/
H A Dxlnx-zynqmp.h39 #include "hw/nvram/xlnx-zynqmp-efuse.h"
113 XlnxEFuse efuse; member
H A Dxlnx-versal.h28 #include "hw/nvram/xlnx-versal-efuse.h"
123 XlnxEFuse efuse; member
/qemu/hw/arm/
H A Dxlnx-versal.c457 object_property_set_link(OBJECT(part), "efuse", in versal_realize_efuse_part()
458 OBJECT(&s->pmc.efuse), &error_abort); in versal_realize_efuse_part()
467 Object *bits = OBJECT(&s->pmc.efuse); in versal_create_efuse()
471 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, in versal_create_efuse()
474 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, in versal_create_efuse()
477 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, in versal_create_efuse()
478 sizeof(s->pmc.efuse), in versal_create_efuse()
480 "efuse-nr", "3", in versal_create_efuse()
481 "efuse-size", "8192", in versal_create_efuse()
H A Dxlnx-zynqmp.c274 Object *bits = OBJECT(&s->efuse); in xlnx_zynqmp_create_efuse()
278 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, in xlnx_zynqmp_create_efuse()
281 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, in xlnx_zynqmp_create_efuse()
282 sizeof(s->efuse), in xlnx_zynqmp_create_efuse()
284 "efuse-nr", "3", in xlnx_zynqmp_create_efuse()
285 "efuse-size", "2048", in xlnx_zynqmp_create_efuse()
289 object_property_set_link(ctrl, "efuse", bits, &error_abort); in xlnx_zynqmp_create_efuse()
H A Dxlnx-zcu102.c172 /* Attach efuse backend, if given */ in xlnx_zcu102_init()
173 efuse_attach_drive(&s->soc.efuse); in xlnx_zcu102_init()
H A Dxlnx-versal-virt.c728 /* Attach efuse backend, if given */ in versal_virt_init()
729 efuse_attach_drive(&s->soc.pmc.efuse); in versal_virt_init()
H A Dxilinx_zynq.c404 create_unimplemented_device("zynq.efuse", 0xF800d000, 0x20); in zynq_init()