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/qemu/qapi/
H A Dcxl.json201 # locally detected errors (e.g. ECC failure) or poisoned writes
224 # @cache-data-parity: Data error such as data parity or data ECC error
233 # @cache-data-ecc: ECC error on CXL.cache
235 # @mem-data-parity: Data error such as data parity or data ECC error
244 # @mem-data-ecc: Data ECC error on CXL.mem.
268 'cache-data-ecc',
272 'mem-data-ecc',
322 # @cache-data-ecc: Data ECC error on CXL.cache
324 # @mem-data-ecc: Data ECC error on CXL.mem
341 'data': ['cache-data-ecc',
[all …]
/qemu/hw/misc/
H A Deccmemctl.c2 * QEMU Sparc Sun4m ECC memory controller emulation
59 /* ECC fault control register */
60 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
81 /* ECC memory delay register */
91 /* ECC fault status register */
101 /* ECC fault address register 0 */
112 /* ECC diagnostic register */
272 .name ="ECC",
310 memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); in ecc_init()
323 "ecc.diag", ECC_DIAG_SIZE); in ecc_realize()
H A Dstm32l4x5_syscfg.c178 /* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/ in stm32l4x5_syscfg_write()
/qemu/include/hw/nvram/
H A Dnpcm7xx_otp.h67 * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
71 * @len: Number of bytes before ECC encoding.
/qemu/include/hw/ppc/
H A Dpnv_xive.h79 * These are in a SRAM protected by ECC.
151 * These are in a SRAM protected by ECC.
/qemu/target/s390x/
H A Dcpu_features_def.h.inc332 DEF_FEAT(PCKMO_ECC_P256, "pckmo-ecc-p256", PCKMO, 32, "PCKMO Encrypt-ECC-P256-Key")
333 DEF_FEAT(PCKMO_ECC_P384, "pckmo-ecc-p384", PCKMO, 33, "PCKMO Encrypt-ECC-P384-Key")
334 DEF_FEAT(PCKMO_ECC_P521, "pckmo-ecc-p521", PCKMO, 34, "PCKMO Encrypt-ECC-P521-Key")
335 DEF_FEAT(PCKMO_ECC_ED25519, "pckmo-ecc-ed25519", PCKMO, 40 , "PCKMO Encrypt-ECC-Ed25519-Key")
336 DEF_FEAT(PCKMO_ECC_ED448, "pckmo-ecc-ed448", PCKMO, 41 , "PCKMO Encrypt-ECC-Ed448-Key")
/qemu/hw/ssi/
H A Dpnv_spi.c130 * Adding an ECC count let's us know when we have found a payload byte in spi_response()
133 * indicate that we are taking in data with ECC and either applying in spi_response()
134 * the ECC or discarding it. in spi_response()
144 * shifted into RDR so we can discard every 9th byte when ECC is in spi_response()
298 * of the shift register, 64 bits or 72 bits if ECC is enabled. in calculate_N1()
307 "ECC enabled, bytes = 0x%x, bits = 0x%x\n", in calculate_N1()
530 * known size of the shift register, 64 bits or 72 bits if ECC in calculate_N2()
539 /* Unsupported N2 shift size when ECC enabled */ in calculate_N2()
/qemu/include/hw/misc/
H A Dnpcm_gcr.h31 * 5: ECC disabled.
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h255 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
298 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
306 #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
315 #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
499 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
/qemu/hw/i2c/
H A Dsmbus_eeprom.c266 /* DIMM configuration 0 = non-ECC */ in spd_data_generate()
269 /* ECC SDRAM width */ in spd_data_generate()
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h270 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
316 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
324 #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
333 #define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
520 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py2511 0x05: '32-bit ECC',
512 0x06: '64-bit ECC',
513 0x07: '128-bit ECC',
633 0x05: 'Single-bit ECC',
634 0x06: 'Multi-bit ECC'
1039 0x01: 'Single-bit ECC memory error',
1040 0x02: 'Multi-bit ECC memory error',
1121 0x05: "Single-bit ECC",
1122 0x06: "Multi-bit ECC",
/qemu/hw/pci-host/
H A Dgt64120.c137 /* ECC */
549 /* ECC */ in gt64120_writel()
750 /* ECC */ in gt64120_readl()
1126 /* ECC */ in gt64120_reset()
/qemu/hw/ppc/
H A Dppc440_bamboo.c180 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ in bamboo_init()
H A Dsam460ex.c337 /* FIXME: does 460EX have ECC interrupts? */ in sam460ex_init()
H A Dppc4xx_sdram.c376 s->ecccfg = 0; /* No ECC */ in ppc4xx_sdram_ddr_reset()
/qemu/docs/devel/
H A Dkconfig.rst250 select ECC
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h348 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
602 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts74 xlnx,ecc-use-ce-exception = < 0x00 >;
/qemu/hw/ide/
H A Dide-internal.h44 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
/qemu/hw/sparc/
H A Dsun4m.c851 /* models without ECC don't trap when missing ram is accessed */ in sun4m_hw_init()
853 empty_slot_init("ecc", machine->ram_size, in sun4m_hw_init()
/qemu/target/sparc/
H A Dasi.h93 #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h330 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h302 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h365 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */

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