| /linux-5.10/drivers/dma/dw-edma/ |
| D | dw-edma-v0-core.c | 11 #include "dw-edma-core.h"
12 #include "dw-edma-v0-core.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-v0-debugfs.h"
26 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
28 return dw->rg_region.vaddr; in __dw_regs()
31 #define SET(dw, name, value) \ argument
32 writel(value, &(__dw_regs(dw)->name))
34 #define GET(dw, name) \ argument
35 readl(&(__dw_regs(dw)->name))
[all …]
|
| D | dw-edma-pcie.c | 17 #include "dw-edma-core.h"
73 struct dw_edma *dw; in dw_edma_pcie_probe() local
123 dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL); in dw_edma_pcie_probe()
124 if (!dw) in dw_edma_pcie_probe()
137 chip->dw = dw; in dw_edma_pcie_probe()
142 dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar]; in dw_edma_pcie_probe()
143 dw->rg_region.vaddr += pdata->rg_off; in dw_edma_pcie_probe()
144 dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; in dw_edma_pcie_probe()
145 dw->rg_region.paddr += pdata->rg_off; in dw_edma_pcie_probe()
146 dw->rg_region.sz = pdata->rg_sz; in dw_edma_pcie_probe()
[all …]
|
| D | dw-edma-core.c | 20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
68 struct dw_edma *dw = chan->chip->dw; in dw_edma_alloc_chunk() local
84 chunk->ll_region.paddr = dw->ll_region.paddr + chan->ll_off; in dw_edma_alloc_chunk()
85 chunk->ll_region.vaddr = dw->ll_region.vaddr + chan->ll_off; in dw_edma_alloc_chunk()
550 struct dw_edma *dw = dw_irq->dw; in dw_edma_interrupt() local
556 total = dw->wr_ch_cnt; in dw_edma_interrupt()
560 total = dw->rd_ch_cnt; in dw_edma_interrupt()
561 off = dw->wr_ch_cnt; in dw_edma_interrupt()
565 val = dw_edma_v0_core_status_done_int(dw, write ? in dw_edma_interrupt()
[all …]
|
| D | Makefile | 3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
5 dw-edma-objs := dw-edma-core.o \
6 dw-edma-v0-core.o $(dw-edma-y)
7 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
|
| D | dw-edma-v0-debugfs.c | 12 #include "dw-edma-v0-debugfs.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-core.h"
42 static struct dw_edma *dw; variable
58 if (dw->mode == EDMA_MODE_LEGACY && in dw_edma_debugfs_u32_get()
65 for (ch = 0; ch < dw->wr_ch_cnt; ch++) in dw_edma_debugfs_u32_get()
71 for (ch = 0; ch < dw->rd_ch_cnt; ch++) in dw_edma_debugfs_u32_get()
83 raw_spin_lock_irqsave(&dw->lock, flags); in dw_edma_debugfs_u32_get()
88 raw_spin_unlock_irqrestore(&dw->lock, flags); in dw_edma_debugfs_u32_get()
177 if (dw->mode == EDMA_MODE_UNROLL) { in dw_edma_debugfs_regs_wr()
[all …]
|
| /linux-5.10/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi-ahb-audio.c | 21 #include "dw-hdmi-audio.h"
23 #define DRIVER_NAME "dw-hdmi-ahb-audio"
153 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_iec958() argument
156 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_iec958()
157 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_iec958()
158 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_iec958()
181 static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_s24() argument
184 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_s24()
185 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_s24()
186 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_s24()
[all …]
|
| /linux-5.10/drivers/dma/dw/ |
| D | core.c | 82 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get() local
86 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); in dwc_desc_get()
101 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_put() local
109 dma_pool_free(dw->desc_pool, child, child->txd.phys); in dwc_desc_put()
113 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); in dwc_desc_put()
119 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_initialize() local
121 dw->initialize_chan(dwc); in dwc_initialize()
124 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
125 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
141 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) in dwc_chan_disable() argument
[all …]
|
| D | idma32.c | 88 static void idma32_set_device_name(struct dw_dma *dw, int id) in idma32_set_device_name() argument
90 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id); in idma32_set_device_name()
99 static void idma32_fifo_partition(struct dw_dma *dw) in idma32_fifo_partition() argument
112 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); in idma32_fifo_partition()
113 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); in idma32_fifo_partition()
116 static void idma32_disable(struct dw_dma *dw) in idma32_disable() argument
118 do_dw_dma_off(dw); in idma32_disable()
119 idma32_fifo_partition(dw); in idma32_disable()
122 static void idma32_enable(struct dw_dma *dw) in idma32_enable() argument
124 idma32_fifo_partition(dw); in idma32_enable()
[all …]
|
| D | dw.c | 16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan() local
23 cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl); in dw_dma_initialize_chan()
91 static void dw_dma_set_device_name(struct dw_dma *dw, int id) in dw_dma_set_device_name() argument
93 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", id); in dw_dma_set_device_name()
96 static void dw_dma_disable(struct dw_dma *dw) in dw_dma_disable() argument
98 do_dw_dma_off(dw); in dw_dma_disable()
101 static void dw_dma_enable(struct dw_dma *dw) in dw_dma_enable() argument
103 do_dw_dma_on(dw); in dw_dma_enable()
108 struct dw_dma *dw; in dw_dma_probe() local
110 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); in dw_dma_probe()
[all …]
|
| D | internal.h | 11 #include <linux/dma/dw.h>
18 void do_dw_dma_on(struct dw_dma *dw);
19 void do_dw_dma_off(struct dw_dma *dw);
27 void dw_dma_acpi_controller_register(struct dw_dma *dw);
28 void dw_dma_acpi_controller_free(struct dw_dma *dw);
30 static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} in dw_dma_acpi_controller_register() argument
31 static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {} in dw_dma_acpi_controller_free() argument
38 void dw_dma_of_controller_register(struct dw_dma *dw);
39 void dw_dma_of_controller_free(struct dw_dma *dw);
45 static inline void dw_dma_of_controller_register(struct dw_dma *dw) {} in dw_dma_of_controller_register() argument
[all …]
|
| /linux-5.10/drivers/dma/dw-axi-dmac/ |
| D | dw-axi-dmac-platform.c | 26 #include "dw-axi-dmac.h"
31 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
179 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { in axi_dma_hw_init()
180 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in axi_dma_hw_init()
181 axi_chan_disable(&chip->dw->chan[i]); in axi_dma_hw_init()
188 u32 max_width = chan->chip->dw->hdata->m_data_width; in axi_chan_get_xfer_width()
200 struct dw_axi_dma *dw = chan->chip->dw; in axi_desc_get() local
204 desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); in axi_desc_get()
222 struct dw_axi_dma *dw = chan->chip->dw; in axi_desc_put() local
228 dma_pool_free(dw->desc_pool, child, child->vd.tx.phys); in axi_desc_put()
[all …]
|
| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
|
| D | rockchip-dw-mshc.yaml | 4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
12 This file documents the combined properties for the core Synopsys dw mshc
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: "synopsys-dw-mshc-common.yaml#"
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
33 - rockchip,px30-dw-mshc
35 - rockchip,rk3036-dw-mshc
37 - rockchip,rk3228-dw-mshc
39 - rockchip,rk3308-dw-mshc
[all …]
|
| D | k3-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
30 compatible = "hisilicon,hi4511-dw-mshc";
55 compatible = "hisilicon,hi6220-dw-mshc";
|
| /linux-5.10/include/uapi/scsi/ |
| D | scsi_bsg_ufs.h | 18 /* uic commands are 4DW long, per UFSHCI V2.1 paragraph 5.6.1 */
23 * @dword_0: UPIU header DW-0
24 * @dword_1: UPIU header DW-1
25 * @dword_2: UPIU header DW-2
42 * @value: Attribute value to be written DW-5
43 * @reserved: spec reserved DW-6,7
58 * @data_transfer_len: Data Transfer Length DW-3
59 * @cdb: Command Descriptor Block CDB DW-4 to DW-7
68 * @header:UPIU header structure DW-0 to DW-2
69 * @sc: fields structure for scsi command DW-3 to DW-7
[all …]
|
| /linux-5.10/drivers/staging/rtl8192u/ |
| D | r819xU_cmdpkt.h | 93 /* DW 0 */
98 /* DW 1 */
102 /* DW 2 */
106 /* DW 3 */
110 /* DW 4 */
114 /* DW 5 */
118 /* DW 6-8 */
123 /* DW 9 */
133 /* DW 0 */
138 /* DW 1-?? */
[all …]
|
| /linux-5.10/arch/arm/boot/dts/ |
| D | berlin2cd.dtsi | 175 compatible = "snps,dw-apb-gpio";
181 compatible = "snps,dw-apb-gpio-port";
193 compatible = "snps,dw-apb-gpio";
199 compatible = "snps,dw-apb-gpio-port";
211 compatible = "snps,dw-apb-gpio";
217 compatible = "snps,dw-apb-gpio-port";
229 compatible = "snps,dw-apb-gpio";
235 compatible = "snps,dw-apb-gpio-port";
267 compatible = "snps,dw-apb-ssi";
277 compatible = "snps,dw-wdt";
[all …]
|
| D | berlin2.dtsi | 185 compatible = "snps,dw-apb-gpio";
191 compatible = "snps,dw-apb-gpio-port";
203 compatible = "snps,dw-apb-gpio";
209 compatible = "snps,dw-apb-gpio-port";
221 compatible = "snps,dw-apb-gpio";
227 compatible = "snps,dw-apb-gpio-port";
239 compatible = "snps,dw-apb-gpio";
245 compatible = "snps,dw-apb-gpio-port";
257 compatible = "snps,dw-apb-timer";
266 compatible = "snps,dw-apb-timer";
[all …]
|
| D | berlin2q.dtsi | 246 compatible = "snps,dw-apb-gpio";
252 compatible = "snps,dw-apb-gpio-port";
264 compatible = "snps,dw-apb-gpio";
270 compatible = "snps,dw-apb-gpio-port";
282 compatible = "snps,dw-apb-gpio";
288 compatible = "snps,dw-apb-gpio-port";
300 compatible = "snps,dw-apb-gpio";
306 compatible = "snps,dw-apb-gpio-port";
342 compatible = "snps,dw-apb-timer";
350 compatible = "snps,dw-apb-timer";
[all …]
|
| /linux-5.10/arch/arm64/boot/dts/synaptics/ |
| D | berlin4ct.dtsi | 134 compatible = "snps,dw-apb-gpio";
140 compatible = "snps,dw-apb-gpio-port";
152 compatible = "snps,dw-apb-gpio";
158 compatible = "snps,dw-apb-gpio-port";
170 compatible = "snps,dw-apb-gpio";
176 compatible = "snps,dw-apb-gpio-port";
188 compatible = "snps,dw-apb-gpio";
194 compatible = "snps,dw-apb-gpio-port";
206 compatible = "snps,dw-apb-ictl";
233 compatible = "snps,dw-apb-ictl";
[all …]
|
| /linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | snps,dw-wdt.yaml | 4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
17 const: snps,dw-wdt
23 description: DW Watchdog pre-timeout interrupt
39 description: Phandle to the DW Watchdog reset lane
45 DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
49 the timer expiration intervals supported by the DW APB Watchdog. Note
50 DW APB Watchdog IP-core might be synthesized with fixed TOP values,
69 compatible = "snps,dw-wdt";
78 compatible = "snps,dw-wdt";
|
| /linux-5.10/drivers/misc/sgi-gru/ |
| D | gruhandles.h | 184 unsigned int cmd:1; /* DW 0 */
199 unsigned long vaddr:64; /* DW 1 */
201 unsigned int asid:24; /* DW 2 */
210 unsigned long vaddrmask:39; /* DW 3 */
259 unsigned int cmd:1; /* DW 0 - low 32*/
274 unsigned int indexway:12; /* DW 0 - high 32 */
280 unsigned long missvaddr:64; /* DW 1 */
282 unsigned int missasid:24; /* DW 2 */
289 unsigned long pfn:41; /* DW 3 */
294 unsigned long fillvaddr:64; /* DW 4 */
[all …]
|
| /linux-5.10/arch/arc/boot/dts/ |
| D | axs10x_mb.dtsi | 55 * DW sdio controller has external ciu clock divider
103 * According to DW Mobile Storage databook it is required
112 * "altr,socfpga-dw-mshc".
116 * "snps,dw-mshc" should be enough for all users of DW MMC once
121 compatible = "altr,socfpga-dw-mshc";
132 compatible = "snps,dw-apb-uart";
142 compatible = "snps,dw-apb-uart";
153 compatible = "snps,dw-apb-uart";
244 compatible = "snps,dw-apb-gpio";
250 compatible = "snps,dw-apb-gpio-port";
[all …]
|
| D | axc003.dtsi | 55 dw-apb-gpio@2000 {
56 compatible = "snps,dw-apb-gpio";
62 compatible = "snps,dw-apb-gpio-port";
74 debug_uart: dw-apb-uart@5000 {
75 compatible = "snps,dw-apb-uart";
120 * The DW APB ICTL intc on MB is connected to CPU intc via a
121 * DT "invisible" DW APB GPIO block, configured to simply pass thru
125 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
126 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
134 compatible = "snps,dw-apb-ictl";
|
| /linux-5.10/drivers/scsi/ufs/ |
| D | ufshci.h | 411 * @base_addr: Lower 32bit physical address DW-0
412 * @upper_addr: Upper 32bit physical address DW-1
413 * @reserved: Reserved for future use DW-2
414 * @size: size of physical segment DW-3
451 * @header: UTRD header DW-0 to DW-3
452 * @command_desc_base_addr_lo: UCD base address low DW-4
453 * @command_desc_base_addr_hi: UCD base address high DW-5
454 * @response_upiu_length: response UPIU length DW-6
455 * @response_upiu_offset: response UPIU offset DW-6
456 * @prd_table_length: Physical region descriptor length DW-7
[all …]
|