26 #include "dw-axi-dmac.h"
31  * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
179 	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {  in axi_dma_hw_init()
180 		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);  in axi_dma_hw_init()
181 		axi_chan_disable(&chip->dw->chan[i]);  in axi_dma_hw_init()
188 	u32 max_width = chan->chip->dw->hdata->m_data_width;  in axi_chan_get_xfer_width()
200 	struct dw_axi_dma *dw = chan->chip->dw;  in axi_desc_get()  local
204 	desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys);  in axi_desc_get()
222 	struct dw_axi_dma *dw = chan->chip->dw;  in axi_desc_put()  local
228 		dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);  in axi_desc_put()
232 	dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);  in axi_desc_put()
275 	u32 priority = chan->chip->dw->hdata->priority[chan->id];  in axi_chan_block_xfer_start()
416 	if (desc->chan->chip->dw->hdata->nr_masters > 1)  in set_desc_dest_master()
437 	max_block_ts = chan->chip->dw->hdata->block_size[chan->id];  in dma_chan_prep_dma_memcpy()
469 		if (chan->chip->dw->hdata->restrict_axi_burst_len) {  in dma_chan_prep_dma_memcpy()
470 			u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;  in dma_chan_prep_dma_memcpy()
598 	struct dw_axi_dma *dw = chip->dw;  in dw_axi_dma_interrupt()  local
607 	for (i = 0; i < dw->hdata->nr_channels; i++) {  in dw_axi_dma_interrupt()
608 		chan = &dw->chan[i];  in dw_axi_dma_interrupt()
761 	chip->dw->hdata->nr_channels = tmp;  in parse_device_properties()
769 	chip->dw->hdata->nr_masters = tmp;  in parse_device_properties()
777 	chip->dw->hdata->m_data_width = tmp;  in parse_device_properties()
780 					     chip->dw->hdata->nr_channels);  in parse_device_properties()
783 	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {  in parse_device_properties()
787 		chip->dw->hdata->block_size[tmp] = carr[tmp];  in parse_device_properties()
791 					     chip->dw->hdata->nr_channels);  in parse_device_properties()
795 	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {  in parse_device_properties()
796 		if (carr[tmp] >= chip->dw->hdata->nr_channels)  in parse_device_properties()
799 		chip->dw->hdata->priority[tmp] = carr[tmp];  in parse_device_properties()
810 		chip->dw->hdata->restrict_axi_burst_len = true;  in parse_device_properties()
811 		chip->dw->hdata->axi_rw_burst_len = tmp - 1;  in parse_device_properties()
821 	struct dw_axi_dma *dw;  in dw_probe()  local
830 	dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);  in dw_probe()
831 	if (!dw)  in dw_probe()
838 	chip->dw = dw;  in dw_probe()
840 	chip->dw->hdata = hdata;  in dw_probe()
863 	dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,  in dw_probe()
864 				sizeof(*dw->chan), GFP_KERNEL);  in dw_probe()
865 	if (!dw->chan)  in dw_probe()
874 	dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,  in dw_probe()
876 	if (!dw->desc_pool) {  in dw_probe()
881 	INIT_LIST_HEAD(&dw->dma.channels);  in dw_probe()
883 		struct axi_dma_chan *chan = &dw->chan[i];  in dw_probe()
891 		vchan_init(&chan->vc, &dw->dma);  in dw_probe()
895 	dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);  in dw_probe()
898 	dw->dma.chancnt = hdata->nr_channels;  in dw_probe()
899 	dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;  in dw_probe()
900 	dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;  in dw_probe()
901 	dw->dma.directions = BIT(DMA_MEM_TO_MEM);  in dw_probe()
902 	dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;  in dw_probe()
904 	dw->dma.dev = chip->dev;  in dw_probe()
905 	dw->dma.device_tx_status = dma_chan_tx_status;  in dw_probe()
906 	dw->dma.device_issue_pending = dma_chan_issue_pending;  in dw_probe()
907 	dw->dma.device_terminate_all = dma_chan_terminate_all;  in dw_probe()
908 	dw->dma.device_pause = dma_chan_pause;  in dw_probe()
909 	dw->dma.device_resume = dma_chan_resume;  in dw_probe()
911 	dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;  in dw_probe()
912 	dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;  in dw_probe()
914 	dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;  in dw_probe()
934 	ret = dmaenginem_async_device_register(&dw->dma);  in dw_probe()
939 		 dw->hdata->nr_channels);  in dw_probe()
952 	struct dw_axi_dma *dw = chip->dw;  in dw_remove()  local
960 	for (i = 0; i < dw->hdata->nr_channels; i++) {  in dw_remove()
961 		axi_chan_disable(&chip->dw->chan[i]);  in dw_remove()
962 		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);  in dw_remove()
971 	list_for_each_entry_safe(chan, _chan, &dw->dma.channels,  in dw_remove()