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/qemu/docs/spin/
H A Dtcg-exclusive.promela45 # warning defaulting to 2 CPU cycles
48 # warning defaulting to 1 CPU cycles
185 byte cycles = 0;
189 :: cycles == N_CYCLES -> break;
191 cycles++;
/qemu/hw/sh4/
H A Dsh7750_regs.h741 #define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */
742 #define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */
743 #define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */
744 #define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */
745 #define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */
746 #define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */
747 #define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */
749 /* SDRAM CAS\ Latency Cycles */
751 #define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */
752 #define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */
[all …]
/qemu/tests/qtest/
H A Dnpcm7xx_adc-test.c169 static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, in adc_calculate_steps() argument
172 return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; in adc_calculate_steps()
181 * ADC should takes roughly 20 cycles to convert one sample. So we assert it in adc_wait_conv_finished()
182 * should take 10~30 cycles here. in adc_wait_conv_finished()
290 /* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
H A Dnpcm7xx_watchdog_timer-test.c171 /* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
186 * cycles passed in test_prescaler()
/qemu/hw/timer/
H A Dnpcm7xx_timer.c75 * The number of clock cycles between interrupt and reset in watchdog, used
165 int64_t cycles) in npcm7xx_watchdog_timer_reset_cycles() argument
167 int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); in npcm7xx_watchdog_timer_reset_cycles()
182 int64_t cycles = 1; in npcm7xx_watchdog_timer_reset() local
187 cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT; in npcm7xx_watchdog_timer_reset()
188 cycles <<= 2 * s; in npcm7xx_watchdog_timer_reset()
190 npcm7xx_watchdog_timer_reset_cycles(t, cycles); in npcm7xx_watchdog_timer_reset()
/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
54 * 1/NPCM7XX_MAX_DUTY cycles.
H A Dnpcm7xx_mft.h50 * @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
/qemu/qapi/
H A Dstats.json46 # @cycles: stat reported in clock cycles.
53 'data' : [ 'bytes', 'seconds', 'cycles', 'boolean' ] }
/qemu/include/qemu/
H A Dtypedefs.h9 * inclusion cycles, in particular for complete struct and union
13 * You can break such cycles and unwanted dependencies by declaring
/qemu/docs/
H A Dmulti-thread-compression.txt27 The process of compression will consume additional CPU cycles, and the
28 extra CPU cycles will increase the migration time. On the other hand,
48 Compression of data will consume extra CPU cycles; so in a system with
/qemu/hw/block/
H A Dm25p80.c999 /* Dummy cycles - modeled with bytes writes instead of bits */ in decode_fast_read_cmd()
1025 * dummy cycles, transmitted via the SI line. in decode_fast_read_cmd()
1027 * The number of dummy cycles is configurable but this is currently in decode_fast_read_cmd()
1031 * of dummy cycles, but this is unsupported at the time being. in decode_fast_read_cmd()
1046 /* Dummy cycles modeled with bytes writes instead of bits */ in decode_dio_read_cmd()
1077 * and dummy cycles, transmitted via the IO1 and IO0 line. in decode_dio_read_cmd()
1079 * The number of dummy cycles is configurable but this is currently in decode_dio_read_cmd()
1095 /* Dummy cycles modeled with bytes writes instead of bits */ in decode_qio_read_cmd()
1127 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. in decode_qio_read_cmd()
1129 * The number of dummy cycles is configurable but this is currently in decode_qio_read_cmd()
[all …]
/qemu/hw/adc/
H A Dnpcm7xx_adc.c74 uint32_t cycles, uint32_t prescaler) in npcm7xx_adc_start_timer() argument
77 int64_t ticks = cycles; in npcm7xx_adc_start_timer()
/qemu/include/hw/adc/
H A Dnpcm7xx_adc.h35 * @conv_timer: The timer counts down remaining cycles for the conversion.
/qemu/include/hw/rtc/
H A Dmc146818rtc_regs.h78 /* period in 32 Khz cycles */ in periodic_period_to_clock()
/qemu/include/hw/timer/
H A Dnpcm7xx_timer.h32 /* The basic watchdog timer period is 2^14 clock cycles. */
/qemu/target/hexagon/imported/
H A Dsystem.idef34 "Enter low-power state for #u8 cycles",{fPAUSE(uiV);})
/qemu/scripts/kvm/
H A Dkvm_flightrecorder32 # consuming CPU cycles. No disk I/O is performed since the ring buffer holds a
/qemu/migration/
H A Dpage_cache.c23 /* the page in cache will not be replaced in two cycles */
/qemu/tests/unit/
H A Drcutorture.c232 int age; /* how many update cycles while not rcu_stress_current */
292 * The updater cycles around updating rcu_stress_current to point at
/qemu/include/hw/xen/interface/
H A Dtrace.h274 uint32_t cycles_included:1; /* u.cycles or u.no_cycles? */
279 } cycles; member
/qemu/tests/uefi-test-tools/UefiTestToolsPkg/BiosTablesTest/
H A DBiosTablesTest.c137 // wasting VCPU cycles while the hypervisor is scanning guest RAM. Second, in BiosTablesTestMain()
/qemu/pc-bios/dtb/
H A Dcanyonlands.dts441 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
442 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
/qemu/hw/ssi/
H A Daspeed_smc.c549 case READ: /* no dummy bytes/cycles */ in aspeed_smc_num_dummies()
592 * No dummy cycles are expected with the current command. Turn in aspeed_smc_do_snoop()
604 /* The SPI transfer has reached the dummy cycles sequence */ in aspeed_smc_do_snoop()
609 /* If no more dummy cycles are expected, turn off snooping */ in aspeed_smc_do_snoop()
617 * Dummy cycles have been faked already. Ignore the current in aspeed_smc_do_snoop()
812 * Register and the read delay cycles in the Read Timing Compensation
/qemu/hw/pci-host/
H A Dppc4xx_pci.c313 /* XXX Interrupt acknowledge cycles not supported. */
/qemu/hw/riscv/
H A Driscv-iommu-hpm.c265 * value + the cycles passed so far. in riscv_iommu_process_iocntinh_cy()

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