/qemu/tests/functional/ |
H A D | test_x86_cpu_model_versions.py | 32 def validate_aliases(self, cpus): argument 33 for c in cpus.values(): 36 self.assertIn(c['alias-of'], cpus, 39 self.assertNotIn('alias-of', cpus[c['alias-of']], 45 def validate_variant_aliases(self, cpus): argument 48 self.assertNotIn("Haswell-noTSX-v1", cpus, 50 self.assertNotIn("Broadwell-noTSX-v1", cpus, 52 self.assertNotIn("Nehalem-IBRS-v1", cpus, 54 self.assertNotIn("Westmere-IBRS-v1", cpus, 56 self.assertNotIn("SandyBridge-IBRS-v1", cpus, [all …]
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/qemu/tests/qtest/ |
H A D | numa-test.c | 28 cli = make_cli(data, "-machine smp.cpus=8 -numa node,nodeid=0,memdev=ram,cpus=0-3 " in test_mon_explicit() 29 "-numa node,nodeid=1,cpus=4-7"); in test_mon_explicit() 33 g_assert(strstr(s, "node 0 cpus: 0 1 2 3")); in test_mon_explicit() 34 g_assert(strstr(s, "node 1 cpus: 4 5 6 7")); in test_mon_explicit() 45 cli = make_cli(data, "-machine smp.cpus=8,smp.sockets=8 " in test_def_cpu_split() 50 g_assert(strstr(s, "node 0 cpus: 0 2 4 6")); in test_def_cpu_split() 51 g_assert(strstr(s, "node 1 cpus: 1 3 5 7")); in test_def_cpu_split() 62 cli = make_cli(data, "-machine smp.cpus=8 " in test_mon_partial() 63 "-numa node,nodeid=0,memdev=ram,cpus=0-1 " in test_mon_partial() 64 "-numa node,nodeid=1,cpus=4-5 "); in test_mon_partial() [all …]
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/qemu/hw/riscv/ |
H A D | numa.c | 40 int i, first_hartid = ms->smp.cpus; in riscv_socket_first_hartid() 46 for (i = 0; i < ms->smp.cpus; i++) { in riscv_socket_first_hartid() 47 if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { in riscv_socket_first_hartid() 55 return (first_hartid < ms->smp.cpus) ? first_hartid : -1; in riscv_socket_first_hartid() 63 return (!socket_id) ? ms->smp.cpus - 1 : -1; in riscv_socket_last_hartid() 66 for (i = 0; i < ms->smp.cpus; i++) { in riscv_socket_last_hartid() 67 if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { in riscv_socket_last_hartid() 75 return (last_hartid < ms->smp.cpus) ? last_hartid : -1; in riscv_socket_last_hartid() 83 return (!socket_id) ? ms->smp.cpus : -1; in riscv_socket_hart_count() 122 if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { in riscv_socket_check_hartids() [all …]
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H A D | shakti_c.c | 65 riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, firmware_load_addr, in shakti_c_machine_state_init() 109 sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); in type_init() 112 (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, in type_init() 151 * - Creates CPUS in riscv_hart_realize(), and can create unintended in shakti_c_soc_class_init() 152 * CPUs in shakti_c_soc_class_init() 162 object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); in shakti_c_soc_instance_init() 170 object_property_set_str(OBJECT(&sss->cpus), "cpu-type", in shakti_c_soc_instance_init() 172 object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, in shakti_c_soc_instance_init()
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H A D | sifive_e.c | 117 riscv_boot_info_init(&boot_info, &s->soc.cpus); in sifive_e_machine_init() 184 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); in type_init() 185 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, in type_init() 187 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); in type_init() 201 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, in sifive_e_soc_realize() 203 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); in sifive_e_soc_realize() 213 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, in sifive_e_soc_realize() 224 0, ms->smp.cpus, false); in sifive_e_soc_realize() 227 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in sifive_e_soc_realize()
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/qemu/hw/openrisc/ |
H A D | openrisc_sim.c | 103 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) in get_cpu_irq() argument 105 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); in get_cpu_irq() 136 qemu_fdt_add_subnode(fdt, "/cpus"); in openrisc_create_fdt() 137 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in openrisc_create_fdt() 138 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in openrisc_create_fdt() 141 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); in openrisc_create_fdt() 172 int num_cpus, OpenRISCCPU *cpus[], in openrisc_sim_net_init() argument 193 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); in openrisc_sim_net_init() 197 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); in openrisc_sim_net_init() 216 OpenRISCCPU *cpus[], int irq_pin) in openrisc_sim_ompic_init() argument [all …]
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H A D | virt.c | 103 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) in get_cpu_irq() argument 105 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); in get_cpu_irq() 108 static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin) in get_per_cpu_irq() argument 117 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); in get_per_cpu_irq() 121 return get_cpu_irq(cpus, 0, irq_pin); in get_per_cpu_irq() 160 qemu_fdt_add_subnode(fdt, "/cpus"); in openrisc_create_fdt() 161 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in openrisc_create_fdt() 162 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in openrisc_create_fdt() 165 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); in openrisc_create_fdt() 201 OpenRISCCPU *cpus[], int irq_pin) in openrisc_virt_ompic_init() argument [all …]
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/qemu/hw/intc/ |
H A D | ompic.c | 52 OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; member 64 return s->cpus[src_cpu].control; in ompic_read() 66 return s->cpus[src_cpu].status; in ompic_read() 78 s->cpus[src_cpu].control = data; in ompic_write() 83 s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING | in ompic_write() 87 qemu_irq_raise(s->cpus[dst_cpu].irq); in ompic_write() 90 s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING; in ompic_write() 91 qemu_irq_lower(s->cpus[src_cpu].irq); in ompic_write() 122 error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); in or1k_ompic_realize() 125 /* Init IRQ sources for all CPUs */ in or1k_ompic_realize() [all …]
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/qemu/hw/core/ |
H A D | machine-smp.c | 68 * Any missing parameter in "cpus/maxcpus/sockets/cores/threads" will be 75 * In the calculation of cpus/maxcpus: When both maxcpus and cpus are omitted, 76 * maxcpus will be computed from the given parameters and cpus will be set 77 * equal to maxcpus. When only one of maxcpus and cpus is given then the 79 * cpus may be specified, but maxcpus must be equal to or greater than cpus. 89 unsigned cpus = config->has_cpus ? config->cpus : 0; in machine_parse_smp_config() local 103 * explicit configuration like "cpus=0" is not allowed. in machine_parse_smp_config() 105 if ((config->has_cpus && config->cpus == 0) || in machine_parse_smp_config() 165 if (cpus == 0 && maxcpus == 0) { in machine_parse_smp_config() 170 maxcpus = maxcpus > 0 ? maxcpus : cpus; in machine_parse_smp_config() [all …]
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/qemu/include/hw/cpu/ |
H A D | cluster.h | 29 * A cluster is a group of CPUs which are all identical and have the same view 33 * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs in an 34 * Arm big.LITTLE system) they should be in different clusters. If the CPUs do 39 * adding the CPUs to it as QOM child objects (e.g. using the 41 * The CPUs may be either direct children of the cluster object, or indirect 44 * All CPUs must be added as children before the cluster is realized. 53 * to be in a cluster with all the other "loose" CPUs, so all CPUs that are
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/qemu/tests/unit/ |
H A D | test-smp-parse.c | 23 #define MIN_CPUS 1 /* set the min CPUs supported by the machine as 1 */ 24 #define MAX_CPUS 4096 /* set the max CPUs supported by the machine as 4096 */ 34 .has_cpus = ha, .cpus = a, \ 43 .cpus = a, \ 57 .has_cpus = ha, .cpus = a, \ 72 .has_cpus = ha, .cpus = a, \ 87 .has_cpus = ha, .cpus = a, \ 103 .has_cpus = true, .cpus = a, \ 133 * topology parameters (i.e. cpus/maxcpus/sockets/cores/threads), 140 * expect: cpus=1,sockets=1,cores=1,threads=1,maxcpus=1 */ [all …]
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/qemu/hw/alpha/ |
H A D | dp264.c | 54 AlphaCPU *cpus[4]; in clipper_init() local 65 unsigned int smp_cpus = machine->smp.cpus; in clipper_init() 67 /* Create up to 4 cpus. */ in clipper_init() 68 memset(cpus, 0, sizeof(cpus)); in clipper_init() 70 cpus[i] = ALPHA_CPU(cpu_create(machine->cpu_type)); in clipper_init() 83 cpus[0]->env.trap_arg0 = ram_size; in clipper_init() 84 cpus[0]->env.trap_arg1 = 0; in clipper_init() 85 cpus[0]->env.trap_arg2 = smp_cpus | (!machine->enable_graphics << 6); in clipper_init() 91 pci_bus = typhoon_init(machine->ram, &isa_irq, &rtc_irq, cpus, in clipper_init() 155 /* Start all cpus at the PALcode RESET entry point. */ in clipper_init() [all …]
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/qemu/docs/system/s390x/ |
H A D | cpu-topology.rst | 67 -smp cpus=5,drawer=1,books=1,sockets=8,cores=4,maxcpus=32 73 -smp cpus=5,sockets=8,cores=4,maxcpus=32 76 inside the topology is calculated by adding the CPUs to the topology 78 book-0, drawer-0 and filling all CPUs of socket-0 before filling socket-1 96 for the ``-device`` argument, like for all CPUs defined with the ``-smp`` 98 adding the CPUs to the topology based on the core-id. 115 New CPUs can be plugged using the device_add hmp command as in: 139 -smp cpus=5,sockets=8,cores=4,maxcpus=32 \ 142 A new CPUs can be plugged using the device_add hmp command as before: 153 * There are 5 CPUs provided to the guest with the ``-smp`` command line [all …]
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/qemu/hw/i386/ |
H A D | x86.c | 65 * all CPUs up to max_cpus. 84 return possible_cpus->cpus[cpu_index].props; in x86_cpu_index_to_props() 96 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, in x86_get_default_cpu_node_id() 126 ms->possible_cpus->cpus[i].type = ms->cpu_type; in x86_possible_cpu_arch_ids() 127 ms->possible_cpus->cpus[i].vcpus_count = 1; in x86_possible_cpu_arch_ids() 128 ms->possible_cpus->cpus[i].arch_id = in x86_possible_cpu_arch_ids() 130 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, in x86_possible_cpu_arch_ids() 132 ms->possible_cpus->cpus[i].props.has_socket_id = true; in x86_possible_cpu_arch_ids() 133 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; in x86_possible_cpu_arch_ids() 135 ms->possible_cpus->cpus[i].props.has_die_id = true; in x86_possible_cpu_arch_ids() [all …]
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H A D | fw_cfg.c | 73 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); in fw_cfg_build_smbios() 127 const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms); in fw_cfg_arch_create() local 140 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", in fw_cfg_arch_create() 144 * "etc/max-cpus" actually being apic_id_limit in fw_cfg_arch_create() 161 for (i = 0; i < cpus->len; i++) { in fw_cfg_arch_create() 162 unsigned int apic_id = cpus->cpus[i].arch_id; in fw_cfg_arch_create() 164 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); in fw_cfg_arch_create() 179 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); in fw_cfg_build_feature_control()
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/qemu/docs/system/ |
H A D | cpu-hotplug.rst | 28 (QEMU) query-hotpluggable-cpus 30 "execute": "query-hotpluggable-cpus", 58 (4) The ``query-hotpluggable-cpus`` command returns an object for CPUs 81 (5) Optionally, run QMP ``query-cpus-fast`` for some details about the 84 (QEMU) query-cpus-fast 87 "execute": "query-cpus-fast",
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H A D | target-arm.rst | 6 QEMU can emulate both 32-bit and 64-bit Arm CPUs. Use the 15 Arm hardware is much more widely varying than x86 hardware. Arm CPUs 25 As well as the more common "A-profile" CPUs (which have MMUs and will 26 run Linux) QEMU also supports "M-profile" CPUs such as the Cortex-M0, 60 the ``virt`` board. ``virt`` supports PCI, virtio, recent CPUs and 61 large amounts of RAM. It also supports 64-bit CPUs.
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/qemu/hw/acpi/ |
H A D | cpu.c | 228 state->devs[i].cpu = CPU(id_list->cpus[i].cpu); in cpu_hotplug_hw_init() 229 state->devs[i].arch_id = id_list->cpus[i].arch_id; in cpu_hotplug_hw_init() 424 cpus_dev = aml_device("\\_SB.CPUS"); in build_cpus_aml() 525 * allows to process CPUs in batches which let us to handle more in build_cpus_aml() 526 * CPUs than CPU_ADDED_LIST can hold. in build_cpus_aml() 537 * Scan CPUs, till there are CPUs with events or in build_cpus_aml() 555 * so next_cpu_cmd continues to find already processed CPUs in build_cpus_aml() 565 * collected CPUs in build_cpus_aml() 580 /* cache added CPUs to Notify/Wakeup later */ in build_cpus_aml() 590 /* cache to be removed CPUs to Notify later */ in build_cpus_aml() [all …]
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/qemu/tests/vm/ |
H A D | conf_example_aarch64.yml | 26 qemu_args: "-smp cpus=16,sockets=2,cores=8 27 -numa node,cpus=0-3,nodeid=0 -numa node,cpus=4-7,nodeid=1 28 -numa node,cpus=8-11,nodeid=2 -numa node,cpus=12-15,nodeid=3
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H A D | conf_example_x86.yml | 27 qemu_args: "-smp cpus=8,sockets=2,cores=4 32 -numa node,cpus=0-1,nodeid=0 -numa node,cpus=2-3,nodeid=1 33 -numa node,cpus=4-5,nodeid=2 -numa node,cpus=6-7,nodeid=3
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/qemu/include/exec/ |
H A D | cputlb.h | 91 * as a convenience for CPUs which don't use memory transaction attributes. 113 * Flush one page from the TLB of all CPUs, for all 116 * When this function returns, no CPUs will subsequently perform 136 * Flush the entire TLB for all CPUs, for all MMU indexes. 138 * When this function returns, no CPUs will subsequently perform 161 * Flush one page from the TLB of all CPUs, for the specified 164 * When this function returns, no CPUs will subsequently perform 186 * Flush all entries from the TLB of all CPUs, for the specified 189 * When this function returns, no CPUs will subsequently perform
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/qemu/hw/arm/ |
H A D | sbsa-ref.c | 243 * From Documentation/devicetree/bindings/arm/cpus.yaml in create_fdt() 247 * * If cpus node's #address-cells property is set to 2 in create_fdt() 255 qemu_fdt_add_subnode(sms->fdt, "/cpus"); in create_fdt() 256 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); in create_fdt() 257 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); in create_fdt() 260 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); in create_fdt() 268 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { in create_fdt() 270 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); in create_fdt() 277 qemu_fdt_add_subnode(sms->fdt, "/cpus/topology"); in create_fdt() 279 qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets); in create_fdt() [all …]
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/qemu/docs/system/arm/ |
H A D | sbsa.rst | 23 - A configurable number of AArch64 CPUs 39 (i.e. CPUs and memory). As a result it must have a firmware specifically built 60 - CPUs 64 - NUMA node id for CPUs and memory 82 Devicetree holds information about CPUs, memory and platform version.
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/qemu/tests/migration-stress/guestperf/ |
H A D | hardware.py | 22 def __init__(self, cpus=1, mem=1, argument 28 self._cpus = cpus 42 "cpus": self._cpus, 57 data["cpus"],
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/qemu/docs/about/ |
H A D | removed-features.rst | 207 possible CPUs. 213 topologies described with -smp include all possible cpus, i.e. 588 documentation of ``query-hotpluggable-cpus`` for additional details. 612 ``query-cpus`` (removed in 6.0) 615 The ``query-cpus`` command is replaced by the ``query-cpus-fast`` command. 617 ``query-cpus-fast`` ``arch`` output member (removed in 6.0) 620 The ``arch`` output member of the ``query-cpus-fast`` command is 773 documentation of ``query-hotpluggable-cpus`` for additional details. 889 System emulator CPUS 899 RISC-V ISA Specific CPUs (removed in 5.1) [all …]
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