| /linux-6.8/drivers/thermal/intel/ |
| D | intel_tcc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
12 * intel_tcc_get_tjmax() - returns the default TCC activation Temperature
13 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
20 int intel_tcc_get_tjmax(int cpu) in intel_tcc_get_tjmax() argument
25 if (cpu < 0) in intel_tcc_get_tjmax()
28 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_tjmax()
34 return val ? val : -ENODATA; in intel_tcc_get_tjmax()
39 * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
40 * @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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| /linux-6.8/tools/testing/selftests/rseq/ |
| D | param_test.c | 1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
245 if (loc_nr_loops == -1 && opt_modulo) { \
246 if (yield_mod_cnt == opt_modulo - 1) { \
302 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
327 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
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| /linux-6.8/arch/arm/mach-zynq/ |
| D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
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| /linux-6.8/Documentation/core-api/ |
| D | this_cpu_ops.rst | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
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| /linux-6.8/drivers/gpio/ |
| D | gpio-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
78 /* The MV78200 has per-CPU registers for edge mask and level mask */
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| /linux-6.8/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
36 cpu = kmap_local_page(page) + offset_in_page(offset); in cpu_set()
39 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
41 *cpu = v; in cpu_set()
44 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
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| /linux-6.8/arch/x86/include/asm/uv/ |
| D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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| /linux-6.8/kernel/time/ |
| D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
[all …]
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| /linux-6.8/tools/testing/selftests/kvm/lib/aarch64/ |
| D | gic_v3.c | 1 // SPDX-License-Identifier: GPL-2.0
39 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
49 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
109 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
117 uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset) in gicv3_reg_readl() argument
121 return readl(base + offset); in gicv3_reg_readl()
124 void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val) in gicv3_reg_writel() argument
128 writel(reg_val, base + offset); in gicv3_reg_writel()
131 uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask) in gicv3_getl_fields() argument
133 return gicv3_reg_readl(cpu_or_dist, offset) & mask; in gicv3_getl_fields()
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| /linux-6.8/drivers/clk/qcom/ |
| D | krait-cc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
[all …]
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| /linux-6.8/drivers/gpu/drm/lima/ |
| D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
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| /linux-6.8/arch/arm/mach-hisi/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
[all …]
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| /linux-6.8/arch/s390/mm/ |
| D | maccess.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Access kernel memory without faulting -- s390 specific implementation.
14 #include <linux/cpu.h>
17 #include <asm/asm-extable.h>
29 unsigned long aligned, offset, count; in s390_kernel_write_odd() local
33 offset = (unsigned long) dst & 7UL; in s390_kernel_write_odd()
34 size = min(8UL - offset, size); in s390_kernel_write_odd()
35 count = size - 1; in s390_kernel_write_odd()
45 : "a" (&tmp), "a" (&tmp[offset]), "a" (src) in s390_kernel_write_odd()
51 * s390_kernel_write - write to kernel memory bypassing DAT
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| /linux-6.8/arch/x86/platform/uv/ |
| D | uv_nmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
37 * Handle system-wide NMI events generated by the global 'power nmi' command.
39 * Basic operation is to field the NMI interrupt on each CPU and wait
40 * until all CPU's have arrived into the nmi handler. If some CPU's do not
50 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
66 /* Non-zero indicates newer SMM NMI handler present */
83 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
91 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
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| /linux-6.8/drivers/media/pci/tw68/ |
| D | tw68-risc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * acknowledged. Full credit goes to them - any problems within this code
25 * @sglist: pointer to "scatter-gather list" of buffer pointers
26 * @offset: offset to target memory buffer
27 * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync
34 unsigned int offset, u32 sync_line, in tw68_risc_field() argument
57 while (offset && offset >= sg_dma_len(sg)) { in tw68_risc_field()
58 offset -= sg_dma_len(sg); in tw68_risc_field()
61 if (bpl <= sg_dma_len(sg) - offset) { in tw68_risc_field()
64 /* (offset<<12) |*/ bpl); in tw68_risc_field()
[all …]
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| /linux-6.8/tools/perf/arch/arm/util/ |
| D | cs-etm.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
69 static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
70 static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu);
73 struct evsel *evsel, int cpu) in cs_etm_validate_context_id() argument
77 struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu; in cs_etm_validate_context_id()
81 u64 contextid = evsel->core.attr.config & in cs_etm_validate_context_id()
90 if (!cs_etm_is_etmv4(itr, cpu)) { in cs_etm_validate_context_id()
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| /linux-6.8/include/linux/ |
| D | relay.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
32 * Per-cpu relay channel buffer
37 void *data; /* start of current sub-buffer */
38 size_t offset; /* current offset into sub-buffer */ member
39 size_t subbufs_produced; /* count of sub-buffers produced */
40 size_t subbufs_consumed; /* count of sub-buffers consumed */
49 size_t *padding; /* padding counts per sub-buffer */
53 unsigned int cpu; /* this buf's cpu */ member
[all …]
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| D | nd.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
41 * struct nvdimm_pmu - data structure for nvdimm perf driver
44 * @cpu: designated cpu for counter access.
45 * @node: node for cpu hotplug notifier link.
46 * @cpuhp_state: state for cpu hotplug notification.
47 * @arch_cpumask: cpumask to get designated cpu for counter access.
52 int cpu; member
72 return -ENXIO; in register_nvdimm_pmu()
94 * struct nd_namespace_common - core infrastructure of a namespace
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| /linux-6.8/arch/mips/boot/dts/mti/ |
| D | sead3.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
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| /linux-6.8/scripts/gdb/linux/ |
| D | cpus.py | 4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
30 if tid > (0x100000000 - MAX_CPUS - 2):
31 return 0x100000000 - tid - 2
33 return tasks.get_thread_info(tasks.get_task_by_pid(tid))['cpu']
35 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
39 def per_cpu(var_ptr, cpu): argument
40 if cpu == -1:
41 cpu = get_current_cpu()
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| /linux-6.8/drivers/crypto/cavium/nitrox/ |
| D | nitrox_isr.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
[all …]
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| /linux-6.8/Documentation/devicetree/bindings/watchdog/ |
| D | qcom-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
10 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
18 - items:
19 - enum:
20 - qcom,kpss-wdt-ipq4019
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| /linux-6.8/drivers/macintosh/ |
| D | windfarm_pm121.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * that none of the code has been re-used, it's a complete
17 * re-implementation
21 * controls with a tiny difference. The control-ids of hard-drive-fan
22 * and cpu-fan is swapped.
28 * new_min = ((((average_power * slope) >> 16) + offset) >> 16) + min_value
34 * offset : -19563152
38 * offset : -15650652
44 * offset : -15650652
48 * offset : -19563152
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| /linux-6.8/include/uapi/drm/ |
| D | v3d_drm.h | 2 * Copyright © 2014-2018 Broadcom
65 /* struct drm_v3d_extension - ioctl extensions
67 * Linked-list of generic extensions where the id identify which struct is
84 /* struct drm_v3d_sem - wait/signal semaphore
108 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
133 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
157 * clients -- that is left up to the submitter to control
165 /* Offset of the render command list.
169 * of tiles (in the case of RCL-only blits).
173 * submitted by other clients -- that is left up to the
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| /linux-6.8/arch/x86/kernel/cpu/mce/ |
| D | amd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
19 #include <linux/cpu.h>
55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
134 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
141 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
142 if (!b->hwid) in smca_get_bank_type()
145 return b->hwid->bank_type; in smca_get_bank_type()
215 * So to define a unique name for each bank, we use a temp c-string to append
[all …]
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