Lines Matching +full:cpu +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
19 #include <linux/cpu.h>
55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
134 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
141 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
142 if (!b->hwid) in smca_get_bank_type()
145 return b->hwid->bank_type; in smca_get_bank_type()
215 * So to define a unique name for each bank, we use a temp c-string to append
227 * A list of the banks enabled on each logical CPU. Controls which respective
244 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
250 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). in smca_set_misc_banks_map()
262 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
266 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
306 smca_set_misc_banks_map(bank, cpu); in smca_configure()
319 if (hwid_mcatype == s_hwid->hwid_mcatype) { in smca_configure()
322 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; in smca_configure()
351 switch (b->address) { in bank4_names()
363 WARN(1, "Funny MSR: 0x%08x\n", b->address); in bank4_names()
389 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " in lvt_off_valid()
390 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, in lvt_off_valid()
391 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
397 * On SMCA CPUs, LVT offset is programmed at a different MSR, and in lvt_off_valid()
398 * the BIOS provides the value. The original field where LVT offset in lvt_off_valid()
404 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " in lvt_off_valid()
406 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
420 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) in threshold_restart_bank()
423 rdmsr(tr->b->address, lo, hi); in threshold_restart_bank()
425 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) in threshold_restart_bank()
426 tr->reset = 1; /* limit cannot be lower than err count */ in threshold_restart_bank()
428 if (tr->reset) { /* reset err count and overflow bit */ in threshold_restart_bank()
431 (THRESHOLD_MAX - tr->b->threshold_limit); in threshold_restart_bank()
432 } else if (tr->old_limit) { /* change limit w/o reset */ in threshold_restart_bank()
434 (tr->old_limit - tr->b->threshold_limit); in threshold_restart_bank()
443 if (!tr->b->interrupt_capable) in threshold_restart_bank()
446 if (tr->set_lvt_off) { in threshold_restart_bank()
447 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { in threshold_restart_bank()
448 /* set new lvt offset */ in threshold_restart_bank()
450 hi |= tr->lvt_off << 20; in threshold_restart_bank()
454 if (tr->b->interrupt_enable) in threshold_restart_bank()
460 wrmsr(tr->b->address, lo, hi); in threshold_restart_bank()
463 static void mce_threshold_block_init(struct threshold_block *b, int offset) in mce_threshold_block_init() argument
468 .lvt_off = offset, in mce_threshold_block_init()
471 b->threshold_limit = THRESHOLD_MAX; in mce_threshold_block_init()
496 int def_offset = -1, def_new; in deferred_error_interrupt_enable()
503 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); in deferred_error_interrupt_enable()
520 unsigned int cpu) in smca_get_block_address() argument
525 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) in smca_get_block_address()
528 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); in smca_get_block_address()
533 unsigned int cpu) in get_block_address() argument
535 u32 addr = 0, offset = 0; in get_block_address() local
537 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) in get_block_address()
541 return smca_get_block_address(bank, block, cpu); in get_block_address()
549 offset = ((low & MASK_BLKPTR_LO) >> 21); in get_block_address()
550 if (offset) in get_block_address()
551 addr = MCG_XBLK_ADDR + offset; in get_block_address()
561 int offset, u32 misc_high) in prepare_threshold_block() argument
563 unsigned int cpu = smp_processor_id(); in prepare_threshold_block() local
569 per_cpu(bank_map, cpu) |= BIT_ULL(bank); in prepare_threshold_block()
572 b.cpu = cpu; in prepare_threshold_block()
588 /* Gather LVT offset for thresholding: */ in prepare_threshold_block()
595 offset = setup_APIC_mce_threshold(offset, new); in prepare_threshold_block()
596 if (offset == new) in prepare_threshold_block()
600 mce_threshold_block_init(&b, offset); in prepare_threshold_block()
603 return offset; in prepare_threshold_block()
608 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in amd_filter_mce()
611 /* See Family 17h Models 10h-2Fh Erratum #1114. */ in amd_filter_mce()
612 if (c->x86 == 0x17 && in amd_filter_mce()
613 c->x86_model >= 0x10 && c->x86_model <= 0x2F && in amd_filter_mce()
614 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) in amd_filter_mce()
618 if (c->x86 < 0x17) { in amd_filter_mce()
619 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) in amd_filter_mce()
628 * - MC4_MISC thresholding is not supported on Family 0x15.
629 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
630 * Models 0x10-0x2F due to Erratum #1114.
639 if (c->x86 == 0x15 && bank == 4) { in disable_err_thresholding()
643 } else if (c->x86 == 0x17 && in disable_err_thresholding()
644 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { in disable_err_thresholding()
671 /* cpu init entry point, called from mce.c with preempt off */
674 unsigned int bank, block, cpu = smp_processor_id(); in mce_amd_feature_init() local
676 int offset = -1; in mce_amd_feature_init() local
681 smca_configure(bank, cpu); in mce_amd_feature_init()
686 address = get_block_address(address, low, high, bank, block, cpu); in mce_amd_feature_init()
700 offset = prepare_threshold_block(bank, block, address, offset, high); in mce_amd_feature_init()
714 return m->bank == 4 && XEC(m->status, 0x1f) == 8; in legacy_mce_is_memory_error()
725 if (XEC(m->status, 0x3f)) in smca_mce_is_memory_error()
728 bank_type = smca_get_bank_type(m->extcpu, m->bank); in smca_mce_is_memory_error()
767 else if (m->bank == 4) in amd_mce_usable_address()
772 if (m->status & MCI_STATUS_POISON) in amd_mce_usable_address()
844 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. in _log_error_deferred()
858 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
899 if (rdmsr_safe(block->address, &low, &high)) in log_and_reset_block()
906 log_error_thresholding(block->bank, ((u64)high << 32) | low); in log_and_reset_block()
922 unsigned int bank, cpu = smp_processor_id(); in amd_threshold_interrupt() local
933 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) in amd_threshold_interrupt()
936 first_block = bp[bank]->blocks; in amd_threshold_interrupt()
945 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) in amd_threshold_interrupt()
963 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
974 if (!b->interrupt_capable) in SHOW_FIELDS()
975 return -EINVAL; in SHOW_FIELDS()
978 return -EINVAL; in SHOW_FIELDS()
980 b->interrupt_enable = !!new; in SHOW_FIELDS()
985 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in SHOW_FIELDS()
986 return -ENODEV; in SHOW_FIELDS()
998 return -EINVAL; in store_threshold_limit()
1006 tr.old_limit = b->threshold_limit; in store_threshold_limit()
1007 b->threshold_limit = new; in store_threshold_limit()
1010 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in store_threshold_limit()
1011 return -ENODEV; in store_threshold_limit()
1020 /* CPU might be offline by now */ in show_error_count()
1021 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) in show_error_count()
1022 return -ENODEV; in show_error_count()
1024 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - in show_error_count()
1025 (THRESHOLD_MAX - b->threshold_limit))); in show_error_count()
1060 ret = a->show ? a->show(b, buf) : -EIO; in show()
1072 ret = a->store ? a->store(b, buf, count) : -EIO; in store()
1090 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) in get_name() argument
1101 bank_type = smca_get_bank_type(cpu, bank); in get_name()
1106 if (b->block < ARRAY_SIZE(smca_umc_block_names)) in get_name()
1107 return smca_umc_block_names[b->block]; in get_name()
1111 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) in get_name()
1116 per_cpu(smca_banks, cpu)[bank].sysfs_id); in get_name()
1120 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, in allocate_threshold_blocks() argument
1147 return -ENOMEM; in allocate_threshold_blocks()
1149 b->block = block; in allocate_threshold_blocks()
1150 b->bank = bank; in allocate_threshold_blocks()
1151 b->cpu = cpu; in allocate_threshold_blocks()
1152 b->address = address; in allocate_threshold_blocks()
1153 b->interrupt_enable = 0; in allocate_threshold_blocks()
1154 b->interrupt_capable = lvt_interrupt_supported(bank, high); in allocate_threshold_blocks()
1155 b->threshold_limit = THRESHOLD_MAX; in allocate_threshold_blocks()
1157 if (b->interrupt_capable) { in allocate_threshold_blocks()
1159 b->interrupt_enable = 1; in allocate_threshold_blocks()
1164 INIT_LIST_HEAD(&b->miscj); in allocate_threshold_blocks()
1167 if (tb->blocks) in allocate_threshold_blocks()
1168 list_add(&b->miscj, &tb->blocks->miscj); in allocate_threshold_blocks()
1170 tb->blocks = b; in allocate_threshold_blocks()
1172 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); in allocate_threshold_blocks()
1176 address = get_block_address(address, low, high, bank, ++block, cpu); in allocate_threshold_blocks()
1180 err = allocate_threshold_blocks(cpu, tb, bank, block, address); in allocate_threshold_blocks()
1185 kobject_uevent(&b->kobj, KOBJ_ADD); in allocate_threshold_blocks()
1191 list_del(&b->miscj); in allocate_threshold_blocks()
1192 kobject_put(&b->kobj); in allocate_threshold_blocks()
1199 struct list_head *head = &b->blocks->miscj; in __threshold_add_blocks()
1204 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); in __threshold_add_blocks()
1210 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); in __threshold_add_blocks()
1213 kobject_del(&pos->kobj); in __threshold_add_blocks()
1221 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, in threshold_create_bank() argument
1227 const char *name = get_name(cpu, bank, NULL); in threshold_create_bank()
1231 return -ENODEV; in threshold_create_bank()
1234 nb = node_to_amd_nb(topology_die_id(cpu)); in threshold_create_bank()
1237 if (nb && nb->bank4) { in threshold_create_bank()
1239 b = nb->bank4; in threshold_create_bank()
1240 err = kobject_add(b->kobj, &dev->kobj, name); in threshold_create_bank()
1245 refcount_inc(&b->cpus); in threshold_create_bank()
1255 err = -ENOMEM; in threshold_create_bank()
1259 /* Associate the bank with the per-CPU MCE device */ in threshold_create_bank()
1260 b->kobj = kobject_create_and_add(name, &dev->kobj); in threshold_create_bank()
1261 if (!b->kobj) { in threshold_create_bank()
1262 err = -EINVAL; in threshold_create_bank()
1267 b->shared = 1; in threshold_create_bank()
1268 refcount_set(&b->cpus, 1); in threshold_create_bank()
1272 WARN_ON(nb->bank4); in threshold_create_bank()
1273 nb->bank4 = b; in threshold_create_bank()
1277 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); in threshold_create_bank()
1285 kobject_put(b->kobj); in threshold_create_bank()
1301 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { in deallocate_threshold_blocks()
1302 list_del(&pos->miscj); in deallocate_threshold_blocks()
1303 kobject_put(&pos->kobj); in deallocate_threshold_blocks()
1306 kobject_put(&bank->blocks->kobj); in deallocate_threshold_blocks()
1314 kobject_put(b->kobj); in __threshold_remove_blocks()
1316 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) in __threshold_remove_blocks()
1317 kobject_put(b->kobj); in __threshold_remove_blocks()
1324 if (!bank->blocks) in threshold_remove_bank()
1327 if (!bank->shared) in threshold_remove_bank()
1330 if (!refcount_dec_and_test(&bank->cpus)) { in threshold_remove_bank()
1335 * The last CPU on this node using the shared bank is going in threshold_remove_bank()
1339 nb->bank4 = NULL; in threshold_remove_bank()
1346 kobject_put(bank->kobj); in threshold_remove_bank()
1364 int mce_threshold_remove_device(unsigned int cpu) in mce_threshold_remove_device() argument
1382 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1383 * @cpu: The plugged in CPU
1387 * This is invoked from the CPU hotplug callback which was installed in
1389 * thread running on @cpu. The callback is invoked on all CPUs which are
1392 int mce_threshold_create_device(unsigned int cpu) in mce_threshold_create_device() argument
1408 return -ENOMEM; in mce_threshold_create_device()
1413 err = threshold_create_bank(bp, cpu, bank); in mce_threshold_create_device()