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/qemu/include/hw/misc/
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
86 * arch/arm/mach-aspeed/include/mach/regs-scu.h
88 * Copyright (C) 2012-2020 ASPEED Technology Inc.
99 * SCU08 Clock Selection Register
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H A Dnpcm7xx_pwm.h19 #include "hw/clock.h"
42 * struct NPCM7xxPWM - The state of a single PWM channel.
52 * @freq: The frequency of this PWM channel.
75 * struct NPCM7xxPWMState - Pulse Width Modulation device state.
78 * @clock: The PWM clock.
82 * @csr: The clock selector register.
92 Clock *clock; member
103 #define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
/qemu/include/hw/
H A Dclock.h4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
22 #define TYPE_CLOCK "clock"
23 OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK)
32 ClockUpdate = 1, /* Clock period has just updated */
33 ClockPreUpdate = 2, /* Clock period is about to update */
39 * clock store a value representing the clock's period in 2^-32ns unit.
41 * + periods from 2^-32ns up to 4seconds
42 * + frequency from ~0.25Hz 2e10Ghz
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H A Dptimer.h17 * using ptimer_run(), the value will count downwards at the frequency
21 * and keep counting down, or to stop (as a one-shot timer).
23 * A transaction-based API is used for modifying ptimer state: all calls
29 * list of state-modifying functions and detailed semantics of the callback.)
31 * Forgetting to set the period/frequency (or setting it to zero) is a
49 * - Starting to run with a period = 0 emits error message and stops the
52 * - Setting period to 0 of the running timer emits error message and
55 * - Starting to run with counter = 0 or setting it to "0" while timer
59 * - Counter value of the running timer is one less than the actual value.
61 * - Changing period/frequency of the running timer loses time elapsed
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/qemu/pc-bios/dtb/
H A Dbamboo.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <0x1fca0550>;
35 timebase-frequency = <0x017d7840>;
36 i-cache-line-size = <0x20>;
37 d-cache-line-size = <0x20>;
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H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
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/qemu/docs/devel/
H A Dclocks.rst1 Modelling a clock tree in QEMU
5 ----------------
10 They allow us to model the clock distribution of a platform and detect
11 configuration errors in the clock tree such as badly configured PLL, clock
12 source selection or disabled clock.
14 The object is *Clock* and its QOM name is ``clock`` (in C code, the macro
21 In these cases a Clock object is a child of a Device object, but this
23 example it is possible to create a clock outside of any device to
24 model the main clock source of a machine.
28 +---------+ +----------------------+ +--------------+
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/qemu/include/hw/timer/
H A Dsse-counter.h14 * the Arm SSE-123 Example Subsystem Technical Reference Manual:
18 * + Clock input "CLK": clock
37 #define TYPE_SSE_COUNTER "sse-counter"
47 Clock *clk;
54 * These are used for handling clock frequency changes: they are a
56 * taken when the clock frequency changes. sse_cntcv() needs them
/qemu/include/standard-headers/linux/
H A Dvmclock-abi.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
4 * This structure provides a vDSO-style clock to VM guests, exposing the
5 * relationship (or lack thereof) between the CPU clock (TSC, timebase, arch
7 * live migration, which other clock enlightenments do not.
9 * When a guest is live migrated, this affects the clock in two ways.
11 * First, even between identical hosts the actual frequency of the underlying
13 * ±50PPM, or 4 seconds a day). This frequency also varies over time on the
15 * live migration there is a step change in the frequency, with no warning.
26 * its clock is invalid and take remedial action. For applications that need
29 * directly for itself that the clock is disrupted and take appropriate
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/qemu/hw/arm/
H A Dnetduinoplus2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
34 /* Main SYSCLK frequency in Hz (168MHz) */
40 Clock *sysclk; in netduinoplus2_init()
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduinoplus2_init()
51 armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu, in netduinoplus2_init()
52 machine->kernel_filename, in netduinoplus2_init()
59 ARM_CPU_TYPE_NAME("cortex-m4"), in netduinoplus2_machine_init()
63 mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; in netduinoplus2_machine_init()
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H A Dnetduino2.c28 #include "hw/qdev-properties.h"
29 #include "hw/qdev-clock.h"
30 #include "qemu/error-report.h"
34 /* Main SYSCLK frequency in Hz (120MHz) */
40 Clock *sysclk; in netduino2_init()
42 /* This clock doesn't need migration because it is fixed-frequency */ in netduino2_init()
51 armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename, in netduino2_init()
58 ARM_CPU_TYPE_NAME("cortex-m3"), in netduino2_machine_init()
62 mc->desc = "Netduino 2 Machine (Cortex-M3)"; in netduino2_machine_init()
63 mc->init = netduino2_init; in netduino2_machine_init()
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H A Dstm32vldiscovery.c29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
37 /* Main SYSCLK frequency in Hz (24MHz) */
43 Clock *sysclk; in stm32vldiscovery_init()
45 /* This clock doesn't need migration because it is fixed-frequency */ in stm32vldiscovery_init()
54 armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu, in stm32vldiscovery_init()
55 machine->kernel_filename, in stm32vldiscovery_init()
62 ARM_CPU_TYPE_NAME("cortex-m3"), in stm32vldiscovery_machine_init()
66 mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; in stm32vldiscovery_machine_init()
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H A Dolimex-stm32-h405.c3 * Olimex STM32-H405 machine
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-clock.h"
31 #include "qemu/error-report.h"
35 /* olimex-stm32-h405 implementation is derived from netduinoplus2 */
37 /* Main SYSCLK frequency in Hz (168MHz) */
43 Clock *sysclk; in olimex_stm32_h405_init()
45 /* This clock doesn't need migration because it is fixed-frequency */ in olimex_stm32_h405_init()
54 armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu, in olimex_stm32_h405_init()
55 machine->kernel_filename, in olimex_stm32_h405_init()
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H A Dstm32f205_soc.c29 #include "system/address-spaces.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/qdev-clock.h"
55 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f205_soc_initfn()
57 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); in stm32f205_soc_initfn()
60 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f205_soc_initfn()
65 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f205_soc_initfn()
69 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); in stm32f205_soc_initfn()
72 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f205_soc_initfn()
76 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f205_soc_initfn()
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H A Dstm32f405_soc.c27 #include "system/address-spaces.h"
30 #include "hw/qdev-clock.h"
61 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f405_soc_initfn()
63 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC); in stm32f405_soc_initfn()
65 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG); in stm32f405_soc_initfn()
68 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f405_soc_initfn()
73 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f405_soc_initfn()
78 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f405_soc_initfn()
82 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f405_soc_initfn()
85 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); in stm32f405_soc_initfn()
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H A Dmsf2-soc.c4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
28 #include "system/address-spaces.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/arm/msf2-soc.h"
32 #include "hw/qdev-clock.h"
66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()
73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); in m2sxxx_soc_initfn()
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H A Dmsf2-som.c4 * M2S-FG484 SOM hardware architecture specification:
5 * https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
31 #include "qemu/error-report.h"
33 #include "hw/qdev-properties.h"
35 #include "hw/qdev-clock.h"
36 #include "system/address-spaces.h"
37 #include "hw/arm/msf2-soc.h"
55 Clock *m3clk; in emcraft_sf2_s2s010_init()
57 memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, in emcraft_sf2_s2s010_init()
63 qdev_prop_set_string(dev, "part-name", "M2S010"); in emcraft_sf2_s2s010_init()
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/qemu/hw/audio/
H A Dfmopl.h10 /* ---------- OPL one of slot ---------- */
22 uint32_t Cnt; /* frequency count : */
23 uint32_t Incr; /* frequency step : */
40 /* ---------- OPL one of channel ---------- */
58 int clock; /* master clock (Hz) */ member
60 double freqbase; /* frequency base */
77 uint32_t FN_TABLE[1024]; /* fnumber -> increment counter */
92 /* ---------- Generic interface section ---------- */
93 FM_OPL *OPLCreate(int clock, int rate);
/qemu/include/hw/rx/
H A Drx62n.h9 * SPDX-License-Identifier: GPL-2.0-or-later
34 #define TYPE_RX62N_MCU "rx62n-mcu"
39 #define TYPE_R5F562N7_MCU "r5f562n7-mcu"
40 #define TYPE_R5F562N8_MCU "r5f562n8-mcu"
71 /* Input Clock (XTAL) frequency */
73 /* Peripheral Module Clock frequency */
/qemu/hw/misc/
H A Dimx_ccm.c2 * IMX31 Clock Control Module
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
8 * See the COPYING file in the top-level directory.
31 uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx_ccm_get_clock_frequency() argument
36 if (klass->get_clock_frequency) { in imx_ccm_get_clock_frequency()
37 freq = klass->get_clock_frequency(dev, clock); in imx_ccm_get_clock_frequency()
40 DPRINTF("(clock = %d) = %u\n", clock, freq); in imx_ccm_get_clock_frequency()
46 * Calculate PLL output frequency
54 uint32_t pd = 1 + PD(pllreg); /* Pre-divider */ in imx_ccm_calc_pll()
60 /* mfn is 10-bit signed twos-complement */ in imx_ccm_calc_pll()
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H A Dzynq_slcr.c25 #include "hw/qdev-clock.h"
27 #include "hw/qdev-properties.h"
188 #define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr"
198 Clock *ps_clk;
199 Clock *uart0_ref_clk;
200 Clock *uart1_ref_clk;
205 * return the output frequency of ARM/DDR/IO pll
206 * using input frequency and PLL_CTRL register
229 /* frequency multiplier -> period division */ in zynq_slcr_compute_pll()
234 * return the output period of a clock given:
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H A Dimx8mp_ccm.c8 * SPDX-License-Identifier: GPL-2.0-or-later
25 memset(s->ccm, 0, sizeof(s->ccm)); in imx8mp_ccm_reset()
91 memory_region_init_io(&s->iomem, in imx8mp_ccm_init()
94 s->ccm, in imx8mp_ccm_init()
96 sizeof(s->ccm)); in imx8mp_ccm_init()
98 sysbus_init_mmio(sd, &s->iomem); in imx8mp_ccm_init()
111 static uint32_t imx8mp_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx8mp_ccm_get_clock_frequency() argument
115 * have fixed frequencies and we can provide requested frequency in imx8mp_ccm_get_clock_frequency()
117 * timer can have its own clock root. in imx8mp_ccm_get_clock_frequency()
123 switch (clock) { in imx8mp_ccm_get_clock_frequency()
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/qemu/hw/ppc/
H A Dsam460ex.c5 * Copyright (c) 2016-2019 BALATON Zoltan
17 #include "qemu/error-report.h"
23 #include "system/block-backend.h"
24 #include "exec/page-protection.h"
29 #include "hw/pci-host/ppc4xx.h"
34 #include "hw/char/serial-mm.h"
38 #include "hw/usb/hcd-ehci.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/intc/ppc-uic.h"
46 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
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/qemu/hw/core/
H A Dqdev-clock.c2 * Device's clock input and output
4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
15 #include "qemu/error-report.h"
16 #include "hw/qdev-clock.h"
17 #include "hw/qdev-core.h"
22 * Add a new clock in a device
25 bool alias, bool output, Clock *clk) in qdev_init_clocklist()
30 * Clock must be added before realize() so that we can compute the in qdev_init_clocklist()
31 * clock's canonical path during device_realize(). in qdev_init_clocklist()
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/qemu/hw/timer/
H A Dcmsdk-apb-timer.c12 /* This is a model of the "APB timer" which is part of the Cortex-M
13 * System Design Kit (CMSDK) and documented in the Cortex-M System
15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
19 * when EXTIN is low), or as a 'timer clock' (timer runs at frequency
20 * of EXTIN clock, not PCLK frequency). We don't model this.
25 * for one clock cycle before reloading from the RELOAD register,
27 * interrupt (as there is no further 1->0 transition).
38 #include "hw/qdev-clock.h"
39 #include "hw/timer/cmsdk-apb-timer.h"
73 qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); in cmsdk_apb_timer_update()
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