Lines Matching +full:clock +full:- +full:frequency
25 #include "hw/qdev-clock.h"
27 #include "hw/qdev-properties.h"
188 #define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr"
198 Clock *ps_clk;
199 Clock *uart0_ref_clk;
200 Clock *uart1_ref_clk;
205 * return the output frequency of ARM/DDR/IO pll
206 * using input frequency and PLL_CTRL register
229 /* frequency multiplier -> period division */ in zynq_slcr_compute_pll()
234 * return the output period of a clock given:
241 * + bits[13:8] clock frequency divisor
242 * + bits[5:4] clock mux selector (index in array)
243 * + bits[index] clock enable
252 /* first, check if clock is disabled */ in zynq_slcr_compute_clock()
260 * "The 6-bit divider provides a divide range of 1 to 63" in zynq_slcr_compute_clock()
264 /* frequency divisor -> period multiplication */ in zynq_slcr_compute_clock()
273 zynq_slcr_compute_clock((plls), (state)->regs[reg], \
278 uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
279 uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
280 uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); in zynq_slcr_compute_clocks_internal()
285 clock_set(s->uart0_ref_clk, in zynq_slcr_compute_clocks_internal()
287 clock_set(s->uart1_ref_clk, in zynq_slcr_compute_clocks_internal()
298 uint64_t ps_clk = clock_get(s->ps_clk); in zynq_slcr_compute_clocks()
315 clock_propagate(s->uart0_ref_clk); in zynq_slcr_propagate_clocks()
316 clock_propagate(s->uart1_ref_clk); in zynq_slcr_propagate_clocks()
334 s->regs[R_LOCKSTA] = 1; in zynq_slcr_reset_init()
335 /* 0x100 - 0x11C */ in zynq_slcr_reset_init()
336 s->regs[R_ARM_PLL_CTRL] = 0x0001A008; in zynq_slcr_reset_init()
337 s->regs[R_DDR_PLL_CTRL] = 0x0001A008; in zynq_slcr_reset_init()
338 s->regs[R_IO_PLL_CTRL] = 0x0001A008; in zynq_slcr_reset_init()
339 s->regs[R_PLL_STATUS] = 0x0000003F; in zynq_slcr_reset_init()
340 s->regs[R_ARM_PLL_CFG] = 0x00014000; in zynq_slcr_reset_init()
341 s->regs[R_DDR_PLL_CFG] = 0x00014000; in zynq_slcr_reset_init()
342 s->regs[R_IO_PLL_CFG] = 0x00014000; in zynq_slcr_reset_init()
344 /* 0x120 - 0x16C */ in zynq_slcr_reset_init()
345 s->regs[R_ARM_CLK_CTRL] = 0x1F000400; in zynq_slcr_reset_init()
346 s->regs[R_DDR_CLK_CTRL] = 0x18400003; in zynq_slcr_reset_init()
347 s->regs[R_DCI_CLK_CTRL] = 0x01E03201; in zynq_slcr_reset_init()
348 s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD; in zynq_slcr_reset_init()
349 s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941; in zynq_slcr_reset_init()
350 s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001; in zynq_slcr_reset_init()
351 s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01; in zynq_slcr_reset_init()
352 s->regs[R_SMC_CLK_CTRL] = 0x00003C01; in zynq_slcr_reset_init()
353 s->regs[R_LQSPI_CLK_CTRL] = 0x00002821; in zynq_slcr_reset_init()
354 s->regs[R_SDIO_CLK_CTRL] = 0x00001E03; in zynq_slcr_reset_init()
355 s->regs[R_UART_CLK_CTRL] = 0x00003F03; in zynq_slcr_reset_init()
356 s->regs[R_SPI_CLK_CTRL] = 0x00003F03; in zynq_slcr_reset_init()
357 s->regs[R_CAN_CLK_CTRL] = 0x00501903; in zynq_slcr_reset_init()
358 s->regs[R_DBG_CLK_CTRL] = 0x00000F03; in zynq_slcr_reset_init()
359 s->regs[R_PCAP_CLK_CTRL] = 0x00000F01; in zynq_slcr_reset_init()
361 /* 0x170 - 0x1AC */ in zynq_slcr_reset_init()
362 s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL] in zynq_slcr_reset_init()
363 = s->regs[R_FPGA2_CLK_CTRL] in zynq_slcr_reset_init()
364 = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800; in zynq_slcr_reset_init()
365 s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA] in zynq_slcr_reset_init()
366 = s->regs[R_FPGA2_THR_STA] in zynq_slcr_reset_init()
367 = s->regs[R_FPGA3_THR_STA] = 0x00010000; in zynq_slcr_reset_init()
369 /* 0x1B0 - 0x1D8 */ in zynq_slcr_reset_init()
370 s->regs[R_BANDGAP_TRIP] = 0x0000001F; in zynq_slcr_reset_init()
371 s->regs[R_PLL_PREDIVISOR] = 0x00000001; in zynq_slcr_reset_init()
372 s->regs[R_CLK_621_TRUE] = 0x00000001; in zynq_slcr_reset_init()
374 /* 0x200 - 0x25C */ in zynq_slcr_reset_init()
375 s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; in zynq_slcr_reset_init()
376 s->regs[R_RST_REASON] = 0x00000040; in zynq_slcr_reset_init()
378 s->regs[R_BOOT_MODE] = s->boot_mode & R_BOOT_MODE_BOOT_MODE_MASK; in zynq_slcr_reset_init()
380 /* 0x700 - 0x7D4 */ in zynq_slcr_reset_init()
382 s->regs[R_MIO + i] = 0x00001601; in zynq_slcr_reset_init()
385 s->regs[R_MIO + i] = 0x00000601; in zynq_slcr_reset_init()
388 s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF; in zynq_slcr_reset_init()
390 s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3] in zynq_slcr_reset_init()
391 = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7] in zynq_slcr_reset_init()
393 s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101; in zynq_slcr_reset_init()
394 s->regs[R_CPU_RAM + 6] = 0x00000001; in zynq_slcr_reset_init()
396 s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2] in zynq_slcr_reset_init()
397 = s->regs[R_IOU + 3] = 0x09090909; in zynq_slcr_reset_init()
398 s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909; in zynq_slcr_reset_init()
399 s->regs[R_IOU + 6] = 0x00000909; in zynq_slcr_reset_init()
401 s->regs[R_DMAC_RAM] = 0x00000009; in zynq_slcr_reset_init()
403 s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909; in zynq_slcr_reset_init()
404 s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909; in zynq_slcr_reset_init()
405 s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909; in zynq_slcr_reset_init()
406 s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909; in zynq_slcr_reset_init()
407 s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2] in zynq_slcr_reset_init()
408 = s->regs[R_AFI3 + 2] = 0x00000909; in zynq_slcr_reset_init()
410 s->regs[R_OCM + 0] = 0x01010101; in zynq_slcr_reset_init()
411 s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909; in zynq_slcr_reset_init()
413 s->regs[R_DEVCI_RAM] = 0x00000909; in zynq_slcr_reset_init()
414 s->regs[R_CSG_RAM] = 0x00000001; in zynq_slcr_reset_init()
416 s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2] in zynq_slcr_reset_init()
417 = s->regs[R_DDRIOB + 3] = 0x00000e00; in zynq_slcr_reset_init()
418 s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] in zynq_slcr_reset_init()
420 s->regs[R_DDRIOB + 12] = 0x00000021; in zynq_slcr_reset_init()
437 zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); in zynq_slcr_reset_exit()
480 case R_MIO ... R_MIO + MIO_LENGTH - 1: in zynq_slcr_check_offset()
489 case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1: in zynq_slcr_check_offset()
496 case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1: in zynq_slcr_check_offset()
508 uint32_t ret = s->regs[offset]; in zynq_slcr_read()
535 s->regs[R_SCL] = val & 0x1; in zynq_slcr_write()
541 s->regs[R_LOCKSTA] = 1; in zynq_slcr_write()
551 s->regs[R_LOCKSTA] = 0; in zynq_slcr_write()
559 if (s->regs[R_LOCKSTA]) { in zynq_slcr_write()
564 s->regs[offset] = val; in zynq_slcr_write()
599 if (s->boot_mode > 0xF) { in zynq_slcr_realize()
600 error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); in zynq_slcr_realize()
608 memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", in zynq_slcr_init()
610 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); in zynq_slcr_init()
627 DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1),
635 dc->vmsd = &vmstate_zynq_slcr; in zynq_slcr_class_init()
636 dc->realize = zynq_slcr_realize; in zynq_slcr_class_init()
637 rc->phases.enter = zynq_slcr_reset_init; in zynq_slcr_class_init()
638 rc->phases.hold = zynq_slcr_reset_hold; in zynq_slcr_class_init()
639 rc->phases.exit = zynq_slcr_reset_exit; in zynq_slcr_class_init()