hw/misc/aspeed_scu.h

9  * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
86  *    arch/arm/mach-aspeed/include/mach/regs-scu.h
88  *    Copyright (C) 2012-2020  ASPEED Technology Inc.
99  * SCU08   Clock Selection Register
101  *  31     Enable Video Engine clock dynamic slow down
102  *  30:28  Video Engine clock slow down setting
103  *  27     2D Engine GCLK clock source selection
104  *  26     2D Engine GCLK clock throttling enable
107  *  19     LPC Host LHCLK clock generation/output enable control
108  *  18:16  MAC AHB bus clock divider selection
109  *  15     SD/SDIO clock running enable
112  *  10:8   Video port output clock delay control bit
113  *  7      ARM CPU/AHB clock slow down enable
114  *  6:4    ARM CPU/AHB clock slow down setting
115  *  3:2    ECLK clock source selection
116  *  1      CPU/AHB clock slow down idle timer
117  *  0      CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
122  * SCU24   H-PLL Parameter Register (for Aspeed AST2400 SOC)
124  *  18     H-PLL parameter selection
125  *           0: Select H-PLL by strapping resistors
126  *           1: Select H-PLL by the programmed registers (SCU24[17:0])
127  *  17     Enable H-PLL bypass mode
128  *  16     Turn off H-PLL
129  *  10:5   H-PLL Numerator
130  *  4      H-PLL Output Divider
131  *  3:0    H-PLL Denumerator
133  *  (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
141  * SCU24   H-PLL Parameter Register (for Aspeed AST2500 SOC)
143  *  21     Enable H-PLL reset
144  *  20     Enable H-PLL bypass mode
145  *  19     Turn off H-PLL
146  *  18:13  H-PLL Post Divider
147  *  12:5   H-PLL Numerator (M)
148  *  4:0    H-PLL Denumerator (N)
150  *  (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
152  * The default frequency is 792Mhz when CLKIN = 24MHz
164  * 23     Enable 25 MHz reference clock input
165  * 22     Enable GPIOE pass-through mode
166  * 21     Enable GPIOD pass-through mode
169  * 23,18  Clock source selection
175  * 11:10  CPU/AHB clock frequency ratio selection
176  * 9:8    H-PLL default clock frequency selection
273  * 23     Select 25 MHz reference clock input mode
274  * 22     Enable GPIOE pass-through mode
275  * 21     Enable GPIOD pass-through mode
278  * 18     Select USBCKI input frequency
284  * 11:9   AXI/AHB clock frequency ratio selection
337  * SCU200   H-PLL Parameter Register (for Aspeed AST2600 SOC)
339  *  28:26  H-PLL Parameters
340  *  25     Enable H-PLL reset
341  *  24     Enable H-PLL bypass mode
342  *  23     Turn off H-PLL
343  *  22:19  H-PLL Post Divider (P)
344  *  18:13  H-PLL Numerator (M)
345  *  12:0   H-PLL Denumerator (N)
347  *  (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
349  * The default frequency is 1200Mhz when CLKIN = 25MHz
359  * SCU310   Clock Selection Register Set 4 (for Aspeed AST1030 SOC)
361  *  31     I3C Clock Source selection
362  *  30:28  I3C clock divider selection
363  *  26:24  MAC AHB clock divider selection
364  *  22:20  RGMII 125MHz clock divider ration
365  *  19:16  RGMII 50MHz clock divider ration
366  *  15     LHCLK clock generation/output enable control
369  *  7      Select PECI clock source
370  *  6      Select UART debug port clock source
371  *  5      Select UART6 clock source
372  *  4      Select UART5 clock source
373  *  3      Select UART4 clock source
374  *  2      Select UART3 clock source
375  *  1      Select UART2 clock source
376  *  0      Select UART1 clock source
381  * SCU280   Clock Selection 1 Register (for Aspeed AST2700 SCUIO)