| /linux-5.10/sound/pci/lola/ |
| D | lola_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
17 unsigned int freq; in lola_sample_rate_convert() local
21 case 0: freq = 48000; break; in lola_sample_rate_convert()
22 case 1: freq = 44100; break; in lola_sample_rate_convert()
23 case 2: freq = 32000; break; in lola_sample_rate_convert()
31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert()
32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert()
33 case (5 << 2): freq /= 2; break; in lola_sample_rate_convert()
34 case (6 << 2): freq /= 4; break; in lola_sample_rate_convert()
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| /linux-5.10/sound/drivers/vx/ |
| D | vx_uer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
67 * vx_write_one_cbit - write one bit to UER config
74 mutex_lock(&chip->lock); in vx_write_one_cbit()
82 mutex_unlock(&chip->lock); in vx_write_one_cbit()
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| /linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
15 Value type: <phandle> From common clock binding.
16 Definition: clock handle for XO clock and GPLL0 clock.
18 - clock-names
20 Value type: <string> From common clock binding.
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
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| /linux-5.10/drivers/gpu/drm/msm/ |
| D | msm_gpu_trace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 __entry->pid = pid;
23 __entry->id = id;
24 __entry->ringid = ringid;
25 __entry->nr_bos = nr_bos;
26 __entry->nr_cmds = nr_cmds
29 __entry->id, __entry->pid, __entry->ringid,
30 __entry->nr_bos, __entry->nr_cmds)
44 __entry->pid = pid_nr(submit->pid);
45 __entry->id = submit->ident;
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| /linux-5.10/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
36 { .compatible = "fsl,mpc5200-cdm", },
46 unsigned int freq; in mpc52xx_can_get_clock() local
52 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
54 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
65 if (!freq) in mpc52xx_can_get_clock()
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| /linux-5.10/drivers/clocksource/ |
| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
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| D | dw_apb_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
51 return readl(timer->base + offs); in apbt_readl()
57 writel(val, timer->base + offs); in apbt_writel()
62 return readl_relaxed(timer->base + offs); in apbt_readl_relaxed()
68 writel_relaxed(val, timer->base + offs); in apbt_writel_relaxed()
80 * dw_apb_clockevent_pause() - stop the clock_event_device from running
82 * @dw_ced: The APB clock to stop generating events.
86 disable_irq(dw_ced->timer.irq); in dw_apb_clockevent_pause()
87 apbt_disable_int(&dw_ced->timer); in dw_apb_clockevent_pause()
100 if (!evt->event_handler) { in dw_apb_clockevent_irq()
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| /linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 34 /* Clock N CTS N CTS N CTS */
51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
57 n = 128 * freq; in amdgpu_afmt_calc_cts()
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts()
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts()
78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
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| /linux-5.10/drivers/sh/clk/ |
| D | core.c | 2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
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| /linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | atmel-pdmic.txt | 4 - compatible
5 Should be "atmel,sama5d2-pdmic".
6 - reg
8 - interrupts
10 - dmas
11 One DMA specifiers as described in atmel-dma.txt and dma.txt files.
12 - dma-names
14 - clock-names
16 - "pclk" peripheral clock
17 - "gclk" generated clock
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| /linux-5.10/drivers/cpufreq/ |
| D | s3c24xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
64 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
65 cfg->freq.armclk = armclk = clk_get_rate(clk_arm); in s3c_cpufreq_getcur()
67 cfg->pll.driver_data = s3c24xx_read_mpllcon(); in s3c_cpufreq_getcur()
68 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
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| D | s3c2412-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/soc/samsung/s3c-cpufreq-core.h>
23 #include <linux/soc/samsung/s3c-pm.h>
41 /* our clock resources. */
55 fclk = cfg->freq.fclk; in s3c2412_cpufreq_calcdivs()
56 armclk = cfg->freq.armclk; in s3c2412_cpufreq_calcdivs()
57 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
68 __func__, cfg->freq.fclk, cfg->freq.armclk, in s3c2412_cpufreq_calcdivs()
69 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
78 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
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| D | armada-8k-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+
34 unsigned int freq[ARRAY_SIZE(opps_div)]; member
37 /* If the CPUs share the same clock, then they are in the same cluster. */
55 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus()
70 unsigned int freq; in armada_8k_add_opp() local
76 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp()
77 return -EINVAL; in armada_8k_add_opp()
83 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp()
85 ret = dev_pm_opp_add(cpu_dev, freq, 0); in armada_8k_add_opp()
89 freq_tables[opps_index].freq[i] = freq; in armada_8k_add_opp()
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| D | qoriq-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
25 * @pclk: the parent clock of cpu
34 * struct soc_data - SoC specific data
48 /* get platform freq by searching bus-frequency property */ in get_bus_freq()
51 ret = of_property_read_u32(soc, "bus-frequency", &sysfreq); in get_bus_freq()
57 /* get platform freq by its clock name */ in get_bus_freq()
58 pltclk = clk_get(NULL, "cg-pll0-div1"); in get_bus_freq()
85 /* traverse cpu nodes to get cpu mask of sharing clock wire */
88 struct cpumask *dstp = policy->cpus; in set_affected_cpus()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 CPU Frequency scaling allows you to change the clock speed of
10 the lower the CPU clock speed, the less power the CPU consumes.
13 clock speed, you need to either enable a dynamic cpufreq governor
16 For details, take a look at <file:Documentation/cpu-freq>.
80 loading your cpufreq low-level hardware driver.
93 loading your cpufreq low-level hardware driver.
143 For details, take a look at <file:Documentation/cpu-freq/>.
151 'ondemand' - This driver adds a dynamic cpufreq policy governor.
161 For details, take a look at linux/Documentation/cpu-freq.
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| /linux-5.10/drivers/net/can/cc770/ |
| D | cc770_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * in your board-specific code:
29 * interrupt-parent = <&mpic>;
30 * bosch,external-clock-frequency = <16000000>;
53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus");
61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
73 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data()
78 prop = of_get_property(np, "bosch,external-clock-frequency", in cc770_get_of_node_data()
84 priv->can.clock.freq = clkext; in cc770_get_of_node_data()
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| /linux-5.10/arch/arm/boot/dts/ |
| D | picoxcell-pc3x3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 cpu-clock = <&arm_clk>, "cpu";
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
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| D | picoxcell-pc3x2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 clock-frequency = <400000000>;
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
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| D | vexpress-v2p-ca5s.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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| /linux-5.10/drivers/clk/hisilicon/ |
| D | clk-hi6220-stub.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hi6220 stub clock driver
11 #include <linux/clk-provider.h>
69 unsigned int freq; in hi6220_acpu_get_freq() local
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
72 return freq; in hi6220_acpu_get_freq()
76 unsigned int freq) in hi6220_acpu_set_freq() argument
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
94 unsigned int freq) in hi6220_acpu_round_freq() argument
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| /linux-5.10/arch/mips/kernel/ |
| D | time.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <asm/cpu-features.h>
25 #include <asm/cpu-type.h>
39 struct cpufreq_freqs *freq = data; in cpufreq_callback() local
40 struct cpumask *cpus = freq->policy->cpus; in cpufreq_callback()
45 * Skip lpj numbers adjustment if the CPU-freq transition is safe for in cpufreq_callback()
48 if (freq->flags & CPUFREQ_CONST_LOOPS) in cpufreq_callback()
54 glb_lpj_ref_freq = freq->old; in cpufreq_callback()
59 per_cpu(pcp_lpj_ref_freq, cpu) = freq->old; in cpufreq_callback()
64 * Adjust global lpj variable and per-CPU udelay_val number in in cpufreq_callback()
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| /linux-5.10/drivers/clk/ti/ |
| D | fapll.c | 13 #include <linux/clk-provider.h>
50 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
80 void __iomem *freq; member
88 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
90 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
98 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
100 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass()
104 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
109 u32 v = readl_relaxed(fd->base); in ti_fapll_clear_bypass()
111 if (fd->bypass_bit_inverted) in ti_fapll_clear_bypass()
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| /linux-5.10/drivers/devfreq/ |
| D | imx8m-ddrc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
50 * +----------+ | | |
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| /linux-5.10/arch/x86/kernel/ |
| D | tsc_msr.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
30 * So we can create a simplified model of the CPU clock setup using a reference
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
62 * Penwell and Clovertrail use spread spectrum clock,
63 * so the freq number is not exactly the same as reported
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
168 u32 lo, hi, ratio, freq, tscref; in cpu_khz_from_msr() local
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| /linux-5.10/arch/arm/mach-sa1100/include/mach/ |
| D | SA-1100.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
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