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/qemu/docs/system/
H A Ddevice-emulation.rst29 Device Buses
33 machine model you choose (``-M foo``) a number of buses will have been
42 additional buses to the system that other devices can be attached to.
/qemu/docs/
H A Dpcie_pci_bridge.txt29 any device plugged in, has no free buses reserved to provide any of them
32 To solve this problem we reserve additional buses on a firmware level.
49 uint32_t bus_res; Minimum number of buses to reserve
H A Dpcie.txt57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
198 Each PCI domain can have up to only 256 buses and the QEMU PCI Express
214 number space. All bus numbers assigned to the buses recursively behind a
222 The PCI Express root buses (pcie.0 and the buses exposed by pxb-pcie devices)
H A Dqdev-device-use.txt6 more buses for children. You can specify a device's parent bus with
9 A device typically has a device address on its parent bus. For buses
33 device. For instance, the IDE controller provides two IDE buses, each
52 TYPE, BUS and UNIT identify the controller device, which of its buses
H A Dpci_expander_bridge.txt8 the main host bridge to support multiple PCI root buses.
/qemu/docs/devel/
H A Dkconfig.rst16 Each QEMU target enables a subset of the boards, devices and buses that
141 **subsystems**, of which **buses** are a special case
153 subsystems or buses. For example, ``AUX`` (the DisplayPort auxiliary
172 have no ``depends on`` directive. Devices also *select* the buses
H A Dreset.rst92 For Devices and Buses, the following helper functions exist:
266 for devices and buses and should be preferred.
358 child buses, and all the devices on those child buses.
H A Dmemory.rst5 The memory API models the memory and I/O buses and controllers of a QEMU
21 buses, memory controllers, and memory regions that have been rerouted.
/qemu/docs/system/devices/
H A Dcan.rst4 emulated CAN controller chips together by one or multiple CAN buses
5 (the controller device "canbus" parameter). The individual buses
9 The concept of buses is generic and different CAN controllers
H A Dusb.rst40 bus though, so there are two completely separate USB buses: One USB
353 same physical port on the host may show up on different host buses
/qemu/include/hw/pci/
H A Dpci_device.h14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
19 /* Implemented by devices that can be plugged on PCI Express buses */
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
H A Dpci_bridge.h171 uint32_t bus_res; /* Minimum number of buses to reserve */
/qemu/docs/specs/
H A Dfsi.rst13 FSI allows a service processor access to the internal buses of a host POWER
22 "engines" that drive accesses on buses internal and external to the POWER
/qemu/hw/pci/
H A Dmeson.build15 # allow plugging PCIe devices into PCI buses, include them even if
/qemu/include/hw/
H A Dqdev-core.h272 * @child_bus: QLIST of child buses
375 * @max_index: max number of child buses
378 * @num_children: current number of child buses
526 * - unrealize any child buses by calling qbus_unrealize()
527 * (this will recursively unrealize any devices on those buses)
1097 * If a machine has multiple buses of a given type, such as I2C,
1098 * where some of those buses in the real hardware are used only for
1100 * can use this function to mark the internal-only buses as full
H A Dresettable.h97 * are the devices on it, and the children of a device are all the buses it
/qemu/hw/acpi/
H A Dpcihp.c78 /* Assign BSEL property only to buses that support hotplug. */
119 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ in acpi_set_pci_info()
157 * below, we generalize this case for all buses, not just the root bus. in acpi_pcihp_find_hotplug_bus()
/qemu/docs/devel/testing/
H A Dqtest.rst31 communicating with system buses or devices. Many virtual device tests use
/qemu/tests/qtest/
H A Dbcm2835-i2c-test.c106 /* Run I2C tests with TMP105 slaves on all three buses */ in main()
/qemu/hw/xen/
H A Dxen-pvh-common.c79 * prepends (not appends) new child buses, the decrementing loop below will in xen_create_virtio_mmio_devices()
80 * create a list of virtio-mmio buses with increasing base addresses. in xen_create_virtio_mmio_devices()
/qemu/docs/system/arm/
H A Dnuvoton.rst87 * I3C buses (8XX only)
/qemu/hw/misc/macio/
H A Dmacio.c180 /* IDE buses */ in macio_oldworld_realize()
285 /* IDE buses */ in macio_newworld_realize()
/qemu/hw/core/
H A Dbus.c2 * Dynamic device configuration and creation -- buses.
/qemu/hw/i2c/
H A Di2c_mux_pca954x.c37 * @channel: The set of i2c channel buses that act as channels which own the
/qemu/hw/ssi/
H A Dxilinx_spips.c256 uint8_t buses; in xlnx_zynqmp_qspips_update_cs_lines() local
259 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); in xlnx_zynqmp_qspips_update_cs_lines()
260 bus0_enabled = buses & 1; in xlnx_zynqmp_qspips_update_cs_lines()
261 bus1_enabled = buses & (1 << 1); in xlnx_zynqmp_qspips_update_cs_lines()

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