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/qemu/hw/ppc/
H A De500.h15 * board supports dynamic sysbus devices
24 /* required -- must at least add toplevel board compatible */
H A Dmpc8544ds.c2 * Support for the PPC e500-based mpc8544ds board
33 error_report("The MPC8544DS board only supports up to 3GB of RAM"); in mpc8544ds_init()
/qemu/docs/system/arm/
H A Dsabrelite.rst4 Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development
31 SABRE Lite board, only exposes a subset of devices to the guest software.
105 blob of the SABRE Lite board. The sample SD card image was populated with the
H A Dvirt.rst6 The ``virt`` board is a platform which does not correspond to any
8 It is the recommended board type if you simply want to run
13 This is a "versioned" board model, so as well as the ``virt`` machine
31 The virt board supports:
235 The ``virt`` board automatically generates a device tree blob ("dtb")
H A Drealview.rst8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
10 QEMU xilinx-zynq-a9 board supports following devices:
/qemu/hw/virtio/
H A DKconfig54 # selected by the board if it has the required support code
66 # selected by the board if it has the required support code
/qemu/hw/riscv/
H A Dsifive_e.c2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
6 * Provides a board compatible with the SiFive Freedom E SDK:
150 mc->desc = "RISC-V Board compatible with SiFive E SDK"; in sifive_e_machine_class_init()
161 "the revB HiFive1 board"); in sifive_e_machine_class_init()
250 /* Pass all GPIOs to the SOC layer so they are available to the board */ in sifive_e_soc_realize()
H A Dxiangshan_kmh.c2 * QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
8 * Provides a board compatible with the Xiangshan Kunminghu
200 mc->desc = "RISC-V Board compatible with the Xiangshan " \ in xiangshan_kmh_machine_class_init()
/qemu/hw/arm/
H A Dkzm.c2 * KZM Board System emulation.
12 * KZM-ARM11-01 evaluation board, with a Freescale
37 * 0xb4001000-0xb400100f Board control IGNORED
H A Dmusca.c2 * Arm Musca-B1 test chip board emulation
15 …arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
16 …arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
17 * We model the A and B1 variants of this board, as described in the TRMs:
114 * Most of the devices in the Musca board sit behind Peripheral Protection
395 * for each CPU in the SSE-200 from each device in the board. in musca_init()
433 * Most of the devices in the board are behind Peripheral Protection in musca_init()
617 mc->desc = "ARM Musca-A board (dual Cortex-M33)"; in musca_a_class_init()
631 mc->desc = "ARM Musca-B1 board (dual Cortex-M33)"; in musca_b1_class_init()
H A Draspi.c35 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
48 * Board revision codes:
134 /* check that we don't overrun board setup vectors */ in write_smpboot()
136 /* check that board setup address is correctly relocated */ in write_smpboot()
147 /* Unlike the AArch32 version we don't need to call the board setup hook. in write_smpboot64()
272 object_property_set_int(OBJECT(soc), "board-rev", board_rev, in raspi_base_machine_init()
H A Dmcimx7d-sabre.c4 * MCIMX7D_SABRE Board System emulation.
11 * It (partially) emulates a mcimx7d_sabre board, with a Freescale
H A Dmcimx6ul-evk.c4 * MCIMX6UL_EVK Board System emulation.
9 * It (partially) emulates a mcimx6ul_evk board, with a Freescale
/qemu/target/arm/
H A Didau.h21 * typically implemented in the SoC which provides board or SoC
24 * QOM interface which is implemented by the board or SoC object and
/qemu/docs/specs/
H A Driscv-iommu.rst29 This will add a RISC-V IOMMU PCI device in the board following any additional
94 For the 'virt' board the device is disabled by default. To enable it use the
102 board using the QEMU command line. The device is configured with the following
/qemu/tests/functional/
H A Dtest_aarch64_sbsaref.py80 # docs/design/trusted-board-boot.rst#trusted-board-boot-sequence
/qemu/docs/system/riscv/
H A Dvirt.rst4 The ``virt`` board is a platform which does not correspond to any real hardware;
5 it is designed for use in virtual machines. It is the recommended board type
90 The board has support for the riscv-iommu-pci device by using the following
236 A TPM device can be connected to the virt board by following the steps below.
/qemu/hw/misc/
H A Dmps2-scc.c170 * These are user-settable DIP switches on the board. We don't in mps2_scc_read()
246 * On some boards bit 0 controls board-specific remapping; in mps2_scc_write()
248 * and let the board wire it up or not as it chooses. in mps2_scc_write()
461 * to the board model or FPGA image)
469 * These are the initial settings for the source clocks on the board.
/qemu/hw/sh4/
H A Dr2d.c303 * According to the old board user document in Japanese (under in r2d_init()
316 /* NIC: rtl8139 on-board, and 2 slots. */ in r2d_init()
325 /* Todo: register on board registers */ in r2d_init()
381 mc->desc = "r2d-plus board"; in r2d_machine_init()
/qemu/hw/tricore/
H A Dtricore_testboard.c34 /* Board init. */
111 mc->desc = "a minimal TriCore board"; in ttb_machine_init()
/qemu/include/hw/arm/
H A Darmv7m.h76 * top of the ones the board provides in board_memory.
100 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
/qemu/include/hw/ppc/
H A Dppc4xx.h118 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
144 uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
/qemu/include/hw/
H A Dboards.h1 /* Declarations for use by board files for creating devices. */
126 * @props - CPU object properties, initialized by board
205 * returns default board specific node_id value for CPU slot specified by
208 * If true, board supports CPUs creation with -device/device_add.
214 * If non-zero, the board promises never to create a CPU with a page size
224 * set only by legacy board models which rely on the old RAZ/WI behaviour
225 * for handling devices that QEMU does not yet model. New board models
251 * If it's not set by board, '-m' will be ignored and generic code will
/qemu/hw/pci-host/
H A Darticia.c21 * This is a minimal emulation of this chip as used in AmigaOne board.
151 * file: board/MAI/AmigaOneG3SE/articiaS_pci.c
158 case 6: /* On board ethernet */ in amigaone_pcihost_bus0_map_irq()

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