1 /*
2 * QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
3 * FPGA prototype platform
4 *
5 * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 * Provides a board compatible with the Xiangshan Kunminghu
9 * FPGA prototype platform:
10 *
11 * 0) UART (16550A)
12 * 1) CLINT (Core-Local Interruptor)
13 * 2) IMSIC (Incoming MSI Controller)
14 * 3) APLIC (Advanced Platform-Level Interrupt Controller)
15 *
16 * More information can be found in our Github repository:
17 * https://github.com/OpenXiangShan/XiangShan
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms and conditions of the GNU General Public License,
21 * version 2 or later, as published by the Free Software Foundation.
22 *
23 * This program is distributed in the hope it will be useful, but WITHOUT
24 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
25 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
26 * more details.
27 *
28 * You should have received a copy of the GNU General Public License along with
29 * this program. If not, see <http://www.gnu.org/licenses/>.
30 */
31
32 #include "qemu/osdep.h"
33 #include "qapi/error.h"
34 #include "system/address-spaces.h"
35 #include "hw/boards.h"
36 #include "hw/char/serial-mm.h"
37 #include "hw/intc/riscv_aclint.h"
38 #include "hw/intc/riscv_aplic.h"
39 #include "hw/intc/riscv_imsic.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/riscv/boot.h"
42 #include "hw/riscv/xiangshan_kmh.h"
43 #include "hw/riscv/riscv_hart.h"
44 #include "system/system.h"
45
46 static const MemMapEntry xiangshan_kmh_memmap[] = {
47 [XIANGSHAN_KMH_ROM] = { 0x1000, 0xF000 },
48 [XIANGSHAN_KMH_UART0] = { 0x310B0000, 0x10000 },
49 [XIANGSHAN_KMH_CLINT] = { 0x38000000, 0x10000 },
50 [XIANGSHAN_KMH_APLIC_M] = { 0x31100000, 0x4000 },
51 [XIANGSHAN_KMH_APLIC_S] = { 0x31120000, 0x4000 },
52 [XIANGSHAN_KMH_IMSIC_M] = { 0x3A800000, 0x10000 },
53 [XIANGSHAN_KMH_IMSIC_S] = { 0x3B000000, 0x80000 },
54 [XIANGSHAN_KMH_DRAM] = { 0x80000000, 0x0 },
55 };
56
xiangshan_kmh_create_aia(uint32_t num_harts)57 static DeviceState *xiangshan_kmh_create_aia(uint32_t num_harts)
58 {
59 int i;
60 const MemMapEntry *memmap = xiangshan_kmh_memmap;
61 hwaddr addr = 0;
62 DeviceState *aplic_m = NULL;
63
64 /* M-level IMSICs */
65 addr = memmap[XIANGSHAN_KMH_IMSIC_M].base;
66 for (i = 0; i < num_harts; i++) {
67 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true,
68 1, XIANGSHAN_KMH_IMSIC_NUM_IDS);
69 }
70
71 /* S-level IMSICs */
72 addr = memmap[XIANGSHAN_KMH_IMSIC_S].base;
73 for (i = 0; i < num_harts; i++) {
74 riscv_imsic_create(addr +
75 i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_BITS),
76 i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS,
77 XIANGSHAN_KMH_IMSIC_NUM_IDS);
78 }
79
80 /* M-level APLIC */
81 aplic_m = riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base,
82 memmap[XIANGSHAN_KMH_APLIC_M].size,
83 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
84 1, true, true, NULL);
85
86 /* S-level APLIC */
87 riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base,
88 memmap[XIANGSHAN_KMH_APLIC_S].size,
89 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
90 1, true, false, aplic_m);
91
92 return aplic_m;
93 }
94
xiangshan_kmh_soc_realize(DeviceState * dev,Error ** errp)95 static void xiangshan_kmh_soc_realize(DeviceState *dev, Error **errp)
96 {
97 MachineState *ms = MACHINE(qdev_get_machine());
98 XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(dev);
99 const MemMapEntry *memmap = xiangshan_kmh_memmap;
100 MemoryRegion *system_memory = get_system_memory();
101 uint32_t num_harts = ms->smp.cpus;
102
103 qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts);
104 qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0);
105 qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type",
106 TYPE_RISCV_CPU_XIANGSHAN_KMH);
107 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
108
109 /* AIA */
110 s->irqchip = xiangshan_kmh_create_aia(num_harts);
111
112 /* UART */
113 serial_mm_init(system_memory, memmap[XIANGSHAN_KMH_UART0].base, 2,
114 qdev_get_gpio_in(s->irqchip, XIANGSHAN_KMH_UART0_IRQ),
115 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
116
117 /* CLINT */
118 riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base,
119 0, num_harts, false);
120 riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base +
121 RISCV_ACLINT_SWI_SIZE,
122 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
123 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
124 RISCV_ACLINT_DEFAULT_MTIME,
125 XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ, true);
126
127 /* ROM */
128 memory_region_init_rom(&s->rom, OBJECT(dev), "xiangshan.kunminghu.rom",
129 memmap[XIANGSHAN_KMH_ROM].size, &error_fatal);
130 memory_region_add_subregion(system_memory,
131 memmap[XIANGSHAN_KMH_ROM].base, &s->rom);
132 }
133
xiangshan_kmh_soc_class_init(ObjectClass * klass,const void * data)134 static void xiangshan_kmh_soc_class_init(ObjectClass *klass, const void *data)
135 {
136 DeviceClass *dc = DEVICE_CLASS(klass);
137
138 dc->realize = xiangshan_kmh_soc_realize;
139 dc->user_creatable = false;
140 }
141
xiangshan_kmh_soc_instance_init(Object * obj)142 static void xiangshan_kmh_soc_instance_init(Object *obj)
143 {
144 XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(obj);
145
146 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
147 }
148
149 static const TypeInfo xiangshan_kmh_soc_info = {
150 .name = TYPE_XIANGSHAN_KMH_SOC,
151 .parent = TYPE_DEVICE,
152 .instance_size = sizeof(XiangshanKmhSoCState),
153 .instance_init = xiangshan_kmh_soc_instance_init,
154 .class_init = xiangshan_kmh_soc_class_init,
155 };
156
xiangshan_kmh_soc_register_types(void)157 static void xiangshan_kmh_soc_register_types(void)
158 {
159 type_register_static(&xiangshan_kmh_soc_info);
160 }
type_init(xiangshan_kmh_soc_register_types)161 type_init(xiangshan_kmh_soc_register_types)
162
163 static void xiangshan_kmh_machine_init(MachineState *machine)
164 {
165 XiangshanKmhState *s = XIANGSHAN_KMH_MACHINE(machine);
166 const MemMapEntry *memmap = xiangshan_kmh_memmap;
167 MemoryRegion *system_memory = get_system_memory();
168 hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;
169
170 /* Initialize SoC */
171 object_initialize_child(OBJECT(machine), "soc", &s->soc,
172 TYPE_XIANGSHAN_KMH_SOC);
173 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
174
175 /* Register RAM */
176 memory_region_add_subregion(system_memory,
177 memmap[XIANGSHAN_KMH_DRAM].base,
178 machine->ram);
179
180 /* ROM reset vector */
181 riscv_setup_rom_reset_vec(machine, &s->soc.cpus,
182 start_addr,
183 memmap[XIANGSHAN_KMH_ROM].base,
184 memmap[XIANGSHAN_KMH_ROM].size, 0, 0);
185 if (machine->firmware) {
186 riscv_load_firmware(machine->firmware, &start_addr, NULL);
187 }
188
189 /* Note: dtb has been integrated into firmware(OpenSBI) when compiling */
190 }
191
xiangshan_kmh_machine_class_init(ObjectClass * klass,const void * data)192 static void xiangshan_kmh_machine_class_init(ObjectClass *klass, const void *data)
193 {
194 MachineClass *mc = MACHINE_CLASS(klass);
195 static const char *const valid_cpu_types[] = {
196 TYPE_RISCV_CPU_XIANGSHAN_KMH,
197 NULL
198 };
199
200 mc->desc = "RISC-V Board compatible with the Xiangshan " \
201 "Kunminghu FPGA prototype platform";
202 mc->init = xiangshan_kmh_machine_init;
203 mc->max_cpus = XIANGSHAN_KMH_MAX_CPUS;
204 mc->default_cpu_type = TYPE_RISCV_CPU_XIANGSHAN_KMH;
205 mc->valid_cpu_types = valid_cpu_types;
206 mc->default_ram_id = "xiangshan.kunminghu.ram";
207 }
208
209 static const TypeInfo xiangshan_kmh_machine_info = {
210 .name = TYPE_XIANGSHAN_KMH_MACHINE,
211 .parent = TYPE_MACHINE,
212 .instance_size = sizeof(XiangshanKmhState),
213 .class_init = xiangshan_kmh_machine_class_init,
214 };
215
xiangshan_kmh_machine_register_types(void)216 static void xiangshan_kmh_machine_register_types(void)
217 {
218 type_register_static(&xiangshan_kmh_machine_info);
219 }
220 type_init(xiangshan_kmh_machine_register_types)
221