#
a8b5c10c |
| 11-Jun-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'hw-misc-20250610' of https://github.com/philmd/qemu into staging
Misc HW patches
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmhILpoACgkQ4+MsLN6t # wN
Merge tag 'hw-misc-20250610' of https://github.com/philmd/qemu into staging
Misc HW patches
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmhILpoACgkQ4+MsLN6t # wN4FxA//U3xm1ZJLQnlS+AQp31foxgptVTNej+ZGOfvhYaUSBtFgUhoiXMPJPN4v # pKWBAFgWigaeM9f01T7H55M+Pj0Az2QLZw+Z6Bklu9RjzisZSuIdMZkPWiJXHBFC # 6OMh6pIjyxuYwYltai8gFFP5ENuILETMpFHEfFQtMiAimXhvDKvcQ5Dmi08UcamQ # hOFdia1djmVYIwJCi+V6Mwl/jwql/L1JpBrLyVOFmxGW8p5ZOjJTLL6pC7288dTP # B8Nb9MhWZpbsHiU4GalTOEXQUuAEa/KX9ZhUqW6kLVhguiD5JoCeMhTur40sX+/J # kKl8dSOhHJ0axEII5PxO4XviN1LWC4DATKfXxHjzvwNbJRH4gdBgaf8zqCeuy0TM # 7pOLzyn6ARXoJZTftS9Ezm1MCdCT5eOQ3+YMrLId8M+KBatogJ8uFMRHa8j+khhB # M08FOufxQGQYZsnz9eb+Dexh+Z3/EiUrCJt1X5icJEQ4uwvoo6lwxVnaV1RWYjRX # EnQOvFr38rctDq3UIckBGzfuVmolEc3l/QgENsNb0AIsz0K2P11Xfg3SNnnPBST8 # duFsWD1/nR53wcKrRli0PMezcH/QuUkRqzBlOc2wllcVKJrp71+m2VDClCmH6bBF # gk03V84b96rWkxwrxFB05mOVmdJKxAFAnwRRfIfYp69r9RgHx4A= # =m3BF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 10 Jun 2025 09:09:46 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20250610' of https://github.com/philmd/qemu: (24 commits) hw/net/i82596: Factor configure function out hw/net/i82596: Update datasheet URL hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class hw/gpio/aspeed: Fix definition of AspeedGPIOClass hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClass hw/virtio/virtio-mem: Fix definition of VirtIOMEMClass tests/unit/test-char: Avoid using g_alloca() backends/tpm: Avoid using g_alloca() hw/gpio/pca9552: Avoid using g_newa() hw/core/cpu: Move CacheType to general cpu.h accel/hvf: Fix TYPE_HVF_ACCEL instance size tests/functional: Add a test for the Arduino UNO machine MAINTAINERS: Update Akihiko Odaki's affiliation pc-bios: ensure installed ROMs don't have execute permissions hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources hw/net/fsl_etsec: Set default MAC address hw/ppc/e500: Move clock and TB frequency to machine class hw/hyperv/balloon: Consolidate OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPE ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
ea585b10 |
| 23-May-2025 |
BALATON Zoltan <balaton@eik.bme.hu> |
hw/ppc/e500: Move clock and TB frequency to machine class
Different machines have different frequencies so make this configurable in machine class instead of using a hard coded constant.
Signed-off
hw/ppc/e500: Move clock and TB frequency to machine class
Different machines have different frequencies so make this configurable in machine class instead of using a hard coded constant.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <431166f96ff12ff3dbc670d40544974415f11305.1748012109.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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#
6b829602 |
| 05-Nov-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu into staging
* Various bug fixes * Big cleanup of deprecated machines * Power11 support for spapr * XIVE improvements * Goo
Merge tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu into staging
* Various bug fixes * Big cleanup of deprecated machines * Power11 support for spapr * XIVE improvements * Goodbye to Cedric and David as ppc reviewers, thank you both o7
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmcoEicACgkQZ7MCdqhi # HK5M8Q//fz+ZkJndXkBjb1Oinx+q+eVtNm2JrvcWIsXyhG3K+6VxYPp69H+SRv/Z # TWuUqMQPxq8mhQvBJlDAttp/oaUEiOcCRvs/iUoBN12L4mVxXfdoT88TZ4frN3eP # 8bePq+DW2N/7gpmsJm5CyEZPpcf9AjVHgLRp3KYFkOJ/14uzvuwnocU39gl+2IUh # MXHTedQgMNXaKorJXk1NVdM6NxMuVhOvwxAs6ya2gwhxyA5tteo5PiQOnDJWkejf # xg3RRsNzGYcs1Qg/3kFIf3RfEB0aYbPxROM8IfPaJWKN5KnMggj/JAkHyK1x/V3J # wml7+cB0doMt/yRiuYJhXpyrtOqpvjRWPA6RhxECWW2kwrovv8NAF8IrFnw9NvOQ # QC66ZaaFcbAcFrVT1e/iggU76d01II6m4OAgKcXw+FRHgps4VU9y83j7ApNnNUWN # IXp9hkzoHi5VwX0FrG4ELUr2iEf1HASMvM8EZ/0AxzWj5iNtQB8lFsrEdaGVXyIS # M5JaJeNjCn4koCyYaFSctH5eKtbzIwnGWnDcdTwaOuQ+9itBvY8O+HZalE6sAc5S # kLFZ7i/Ut/qxbY5pMumt8LKD4pR1SsOxFB8dJCmn/f/tvRGtIVsoY6btNe4M0+24 # 42MxZbWO6W379C32bwbtsPiGA+aLSgShjP4cWm9cgRjz4RJFnwg= # =vmIG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 00:15:35 GMT # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu: (67 commits) MAINTAINERS: Remove myself as reviewer MAINTAINERS: Remove myself from XIVE MAINTAINERS: Remove myself from the PowerNV machines hw/ppc: Consolidate ppc440 initial mapping creation functions hw/ppc: Consolidate e500 initial mapping creation functions tests/qtest: Add XIVE tests for the powernv10 machine pnv/xive2: TIMA CI ops using alternative offsets or byte lengths pnv/xive2: TIMA support for 8-byte OS context push for PHYP pnv/xive: Update PIPR when updating CPPR pnv/xive: Add special handling for pool targets ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" ppc/xive2: Change context/ring specific functions to be generic ppc/xive2: Support "Pull Thread Context to Register" operation ppc/xive2: Allow 1-byte write of Target field in TIMA ppc/xive2: Dump the VP-group and crowd tables with 'info pic' ppc/xive2: Dump more NVP state with 'info pic' pnv/xive2: Support for "OS LGS Push" TIMA operation ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" pnv/xive2: Define OGEN field in the TIMA pnv/xive: TIMA patch sets pre-req alignment and formatting changes ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
779a30df |
| 16-Jul-2024 |
BALATON Zoltan <balaton@eik.bme.hu> |
hw/ppc: Consolidate e500 initial mapping creation functions
Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines.
Signed-off-
hw/ppc: Consolidate e500 initial mapping creation functions
Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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#
222059a0 |
| 21-Dec-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-12-21:
This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, t
Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-12-21:
This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board).
# gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
3f288c4b |
| 01-Nov-2022 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ppc/e500: Add Freescale eSDHC to e500plat
Adds missing functionality to e500plat machine which increases the chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Be
hw/ppc/e500: Add Freescale eSDHC to e500plat
Adds missing functionality to e500plat machine which increases the chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221018210146.193159-8-shentey@gmail.com> [PMD: Simplify using create_unimplemented_device("esdhc")] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221101222934.52444-4-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
2c65091f |
| 18-Oct-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-10-18:
This queue contains improvements in the e500 and ppc4xx boards, changes in the maintai
Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-10-18:
This queue contains improvements in the e500 and ppc4xx boards, changes in the maintainership of the project, a new QMP/HMP command and bug fixes:
- Cedric is stepping back from qemu-ppc maintainership; - ppc4xx_sdram: QOMification and clean ups; - e500: add new types of flash and clean ups; - QMP/HMP: introduce dumpdtb command; - spapr_pci, booke doorbell interrupt and xvcmp* bit fixes;
The 'dumpdtb' implementation is also making changes to RISC-V files that were acked by Alistair Francis and are being included in this queue.
# -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCY02qEgAKCRA82cqW3gMx # ZIadAQCYY9f+NFrSJBm3z4JjUaP+GmbgEjibjZW05diyKwbqzQEAjE1KXFCcd40D # 3Brs2Dm4YruaJCwb68vswVQAYteXaQ8= # =hl94 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Oct 2022 15:16:34 EDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu: (38 commits) hw/riscv: set machine->fdt in spike_board_init() hw/riscv: set machine->fdt in sifive_u_machine_init() hw/ppc: set machine->fdt in spapr machine hw/ppc: set machine->fdt in pnv_reset() hw/ppc: set machine->fdt in pegasos2_machine_reset() hw/ppc: set machine->fdt in xilinx_load_device_tree() hw/ppc: set machine->fdt in sam460ex_load_device_tree() hw/ppc: set machine->fdt in bamboo_load_device_tree() hw/nios2: set machine->fdt in nios2_load_dtb() qmp/hmp, device_tree.c: introduce dumpdtb hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset() target/ppc: Fix xvcmp* clearing FI bit hw/ppc/e500: Remove if statement which is now always true hw/ppc/mpc8544ds: Add platform bus hw/ppc/mpc8544ds: Rename wrongly named method hw/ppc/e500: Reduce usage of sysbus API docs/system/ppc/ppce500: Add heading for networking chapter hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx hw/ppc/meson: Allow e500 boards to be enabled separately ppc440_uc.c: Remove unneeded parenthesis ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
9f6621bd |
| 03-Oct-2022 |
Bernhard Beschow <shentey@gmail.com> |
hw/ppc/e500: Remove if statement which is now always true
Now that the MPC8544DS board also has a platform bus, the if statement is always true.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
hw/ppc/e500: Remove if statement which is now always true
Now that the MPC8544DS board also has a platform bus, the if statement is always true.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221003203142.24355-8-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
4dad0a9a |
| 21-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM queue, 2020-09-18
Fixes: * Error value corrections (Markus Armbruster) * Correct object_class_dynamic
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM queue, 2020-09-18
Fixes: * Error value corrections (Markus Armbruster) * Correct object_class_dynamic_cast_assert() documentation (Eduardo Habkost) * Ensure objects using QEMU_ALIGNED are properly aligned (Richard Henderson)
QOM cleanups (Eduardo Habkost): * Rename some constants * Simplify parameters of OBJECT_DECLARE* macros * Additional DECLARE_*CHECKER* usage * Additional OBJECT_DECLARE_TYPE usage * Additional OBJECT_DECLARE_SIMPLE_TYPE usage
# gpg: Signature made Fri 18 Sep 2020 21:45:29 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request: Use OBJECT_DECLARE_SIMPLE_TYPE when possible Use OBJECT_DECLARE_TYPE when possible qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros qom: Remove ParentClassType argument from OBJECT_DECLARE_SIMPLE_TYPE scripts/codeconverter: Update to latest version target/s390x: Set instance_align on S390CPU TypeInfo target/riscv: Set instance_align on RISCVCPU TypeInfo target/ppc: Set instance_align on PowerPCCPU TypeInfo target/arm: Set instance_align on CPUARM TypeInfo qom: Allow objects to be allocated with increased alignment qom: Correct error values in two contracts qom: Clean up object_property_get_enum()'s error value qom: Correct object_class_dynamic_cast_assert() documentation sifive: Use DECLARE_*CHECKER* macros sifive: Move QOM typedefs and add missing includes sifive_u: Rename memmap enum constants sifive_e: Rename memmap enum constants
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a489d195 |
| 16-Sep-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Use OBJECT_DECLARE_TYPE when possible
This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible.
$ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDecl
Use OBJECT_DECLARE_TYPE when possible
This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible.
$ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]')
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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#
f4ef8c9c |
| 11-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM boilerplate cleanup
Documentation build fix: * memory: Remove kernel-doc comment marker (Eduardo Habk
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM boilerplate cleanup
Documentation build fix: * memory: Remove kernel-doc comment marker (Eduardo Habkost)
QOM cleanups: * Rename QOM macros for consistency between TYPE_* and type checking constants (Eduardo Habkost)
QOM new macros: * OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé) * DECLARE_*_CHECKER macros (Eduardo Habkost)
Automated QOM boilerplate changes: * Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost * Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)
# gpg: Signature made Thu 10 Sep 2020 19:17:49 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request: (33 commits) virtio-vga: Use typedef name for instance_size vhost-user-vga: Use typedef name for instance_size xilinx_axienet: Use typedef name for instance_size lpc_ich9: Use typedef name for instance_size omap_intc: Use typedef name for instance_size xilinx_axidma: Use typedef name for instance_size tusb6010: Rename TUSB to TUSB6010 pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312 vfio: Rename PCI_VFIO to VFIO_PCI usb: Rename USB_SERIAL_DEV to USB_SERIAL sabre: Rename SABRE_DEVICE to SABRE rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER esp: Rename ESP_STATE to ESP ahci: Rename ICH_AHCI to ICH9_AHCI vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE gpex: Fix type checking function name ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8110fa1d |
| 31-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Use DECLARE_*CHECKER* macros
Generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé <berrange@redha
Use DECLARE_*CHECKER* macros
Generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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#
db1015e9 |
| 03-Sep-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TY
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName" declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]')
which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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#
f5583c52 |
| 11-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging
target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging
target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension
# gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # target/riscv/translate.c
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a3fc8396 |
| 10-May-2018 |
Igor Mammedov <imammedo@redhat.com> |
platform-bus-device: use device plug callback instead of machine_done notifier
platform-bus were using machine_done notifier to get and map (assign irq/mmio resources) dynamically added sysbus devic
platform-bus-device: use device plug callback instead of machine_done notifier
platform-bus were using machine_done notifier to get and map (assign irq/mmio resources) dynamically added sysbus devices after all '-device' options had been processed. That however creates non obvious dependencies on ordering of machine_done notifiers and requires carefull line juggling to keep it working. For example see comment above create_platform_bus() and 'straitforward' arm_load_kernel() had to converted to machine_done notifier and that lead to yet another machine_done notifier to keep it working arm_register_platform_bus_fdt_creator().
Instead of hiding resource assignment in platform-bus-device to magically initialize sysbus devices, use device plug callback and assign resources explicitly at board level at the moment each -device option is being processed.
That adds a bunch of machine declaration boiler plate to e500plat board, similar to ARM/x86 but gets rid of hidden machine_done notifier and would allow to remove the dependent notifiers in ARM code simplifying it and making code flow easier to follow.
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1525691524-32265-3-git-send-email-imammedo@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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dcbd26f8 |
| 27-Apr-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180427' into staging
ppc patch queue 2018-04-27
Here's the first batch of ppc patches for 2.13. This has a lot of stuff that's acc
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180427' into staging
ppc patch queue 2018-04-27
Here's the first batch of ppc patches for 2.13. This has a lot of stuff that's accumulated during the 2.12 freeze. Highlights are:
* Many improvements for the Uninorth PCI host bridge for Mac machine types * Preliminary helpers improve handling of multiple backing pagesizes (not strictly ppc related, but have acks and aimed to allow future ppc changes) * Cleanups to pseries cpu initialization * Cleanups to hash64 MMU handling * Assorted bugfixes and improvements
# gpg: Signature made Fri 27 Apr 2018 10:20:30 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.13-20180427: (49 commits) Clear mem_path if we fall back to anonymous RAM allocation spapr: Set compatibility mode before the rest of spapr_cpu_reset() target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr() spapr: Support ibm,dynamic-memory-v2 property ppc: e500: switch E500 based machines to full machine definition spapr: Add ibm,max-associativity-domains property target/ppc: Fold slb_nr into PPCHash64Options target/ppc: Get rid of POWERPC_MMU_VER() macros target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model target/ppc: Fold ci_large_pages flag into PPCHash64Options target/ppc: Move 1T segment and AMR options to PPCHash64Options target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs target/ppc: Split page size information into a separate allocation target/ppc: Move page size setup to helper function target/ppc: Remove fallback 64k pagesize information target/ppc: Avoid taking "env" parameter to mmu-hash64 functions target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() target/ppc: Simplify cpu valid check in ppc_cpu_realize target/ppc: Standardize instance_init and realize function names spapr: drop useless dynamic sysbus device sanity check ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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03f04809 |
| 18-Apr-2018 |
Igor Mammedov <imammedo@redhat.com> |
ppc: e500: switch E500 based machines to full machine definition
Convert PPCE500Params to PCCE500MachineClass which it essentially is, and introduce PCCE500MachineState to keep track of E500 specifi
ppc: e500: switch E500 based machines to full machine definition
Convert PPCE500Params to PCCE500MachineClass which it essentially is, and introduce PCCE500MachineState to keep track of E500 specific state instead of adding global variables or extra parameters to functions when we need to keep data beyond machine init (i.e. make it look like typical fully defined machine).
It's pretty shallow conversion instead of currently used trivial DEFINE_MACHINE() macro. It adds extra 60LOC of boilerplate code of full machine definition.
The patch on top[1] will use PCCE500MachineState to keep track of platform_bus device and add E500Plate specific machine class to use HOTPLUG_HANDLER for explicitly initializing dynamic sysbus devices at the time they are added instead of delaying it to machine done time by platform_bus_init_notify() which is being removed.
1) <1523551221-11612-3-git-send-email-imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Suggested-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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1b756f1a |
| 01-Jul-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160701' into staging
ppc patch queue 2016-07-01
Here's the current ppc patch queue. This is a fairly large batch, containing: *
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160701' into staging
ppc patch queue 2016-07-01
Here's the current ppc patch queue. This is a fairly large batch, containing: * A number of further preliminary patches towards full hypervisor mode emulation * Some further fixes / cleanups for the recently merged device_add based CPU hotplug * Preliminary patches towards supporting a native (rather than paravirtualized) XICS device. This will be needed to emulate a physical Power machine, including hypervisor capabilities * Assorted bug fixes
# gpg: Signature made Fri 01 Jul 2016 06:56:35 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.7-20160701: (23 commits) qmp: fix spapr example of query-hotpluggable-cpus spapr: drop duplicate variable in spapr_core_release() spapr: do proper error propagation in spapr_cpu_core_realize_child() spapr: drop reference on child object during core realization spapr: Restore support for 970MP and POWER8NVL CPU cores target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso ppc/xics: Replace "icp" with "xics" in most places ppc/xics: Implement H_IPOLL using an accessor ppc/xics: Move SPAPR specific code to a separate file ppc/xics: Rename existing xics to xics_spapr ppc: Fix 64K pages support in full emulation target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb spapr: Restore support for older PowerPC CPU cores spapr: fix write-past-end-of-array error in cpu core device init code hw/ppc/spapr: Add some missing hcall function set strings ppc: Print HSRR0/HSRR1 in "info registers" ppc: LPCR is a HV resource ppc: Initial HDEC support ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set ppc: Fix conditions for delivering external interrupts to a guest ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a36848ff |
| 28-Jun-2016 |
Aaron Larson <alarson@ddci.com> |
target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb
Eliminate redundant and incorrect booke206_page_size_to_tlb function from ppce500_spin.c in preference to previously
target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb
Eliminate redundant and incorrect booke206_page_size_to_tlb function from ppce500_spin.c in preference to previously existing but newly exported definition from e500.c
Defect analysis:
The booke206_page_size_to_tlb function in e500.c was updated in commit 2bd9543 "ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages" to reflect a change in the definition of MAS1_TSIZE_SHIFT from 8 (corresponding to a min TLB page size of 4kb) to a value of 7 (TLB page size 2k). The booke206_page_size_to_tlb() function defined in ppce500_spin.c was never updated to reflect the change in MAS1_TSIZE_SHIFT.
In http://lists.nongnu.org/archive/html/qemu-ppc/2016-06/msg00533.html, Scott Wood suggested this "root cause" explanation:
SW> The patch that changed MAS1_TSIZE_SHIFT from 8 to 7 was around the SW> same time as the patch that added this code, which is probably why SW> adjusting it got missed. Commit 2bd9543cd3 did update the SW> equivalent code in ppce500_mpc8544ds.c, which now resides in SW> hw/ppc/e500.c and has been changed to not assume a power-of-2 SW> size. The ppce500_spin version should be eliminated.
Signed-off-by: Aaron Larson <alarson@ddci.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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97052d64 |
| 10-Jan-2015 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2015-01-07
New year's release. This time's highlights:
- E500: More RAM support - p
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2015-01-07
New year's release. This time's highlights:
- E500: More RAM support - pseries: New SLOF release - Migration fixes - Simplify USB spawning logic, removes support for explicit usb=off - TCG: Simple untansactional TM emulation
# gpg: Signature made Wed 07 Jan 2015 15:19:37 GMT using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>"
* remotes/agraf/tags/signed-ppc-for-upstream: (37 commits) hw/ppc/mac_newworld: simplify usb controller creation logic hw/ppc/spapr: simplify usb controller creation logic hw/ppc/mac_newworld: QOMified mac99 machines hw/usb: simplified usb_enabled hw/machine: added machine_usb wrapper hw/ppc: modified the condition for usb controllers to be created for some ppc machines target-ppc: Cast ssize_t to size_t before printing with %zx target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY PPC: e500: Fix GPIO controller interrupt number target-ppc: Introduce Privileged TM Noops target-ppc: Introduce tcheck target-ppc: Introduce TM Noops target-ppc: Introduce tbegin target-ppc: Introduce TEXASRU Bit Fields target-ppc: Power8 Supports Transactional Memory target-ppc: Introduce tm_enabled Bit to CPU State target-ppc: Introduce Feature Flag for Transactional Memory target-ppc: Introduce Instruction Type for Transactional Memory pseries: Update SLOF firmware image to 20141202 PPC: Fix crash on spapr_tce_table_finalize() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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cb3778a0 |
| 12-Nov-2014 |
Alexander Graf <agraf@suse.de> |
PPC: e500 pci host: Add support for ATMUs
The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively
PPC: e500 pci host: Add support for ATMUs
The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges.
So far, we've simply assumed that this mapping is 1:1 and ignored it.
However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view.
So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU.
With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM.
Signed-off-by: Alexander Graf <agraf@suse.de>
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2eaaac1f |
| 07-Nov-2014 |
Alexander Graf <agraf@suse.de> |
PPC: e500: Move CCSR definition to params
We want to have different MMIO region offsets for the mpc8544ds machine and our e500 PV machine, so move the definitions of those into the machine specific
PPC: e500: Move CCSR definition to params
We want to have different MMIO region offsets for the mpc8544ds machine and our e500 PV machine, so move the definitions of those into the machine specific params struct.
Signed-off-by: Alexander Graf <agraf@suse.de>
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c8d94330 |
| 04-Nov-2014 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2014-11-04
Fun things for 2.2:
- e500 virt machine: power off support (needs 3.19 gue
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2014-11-04
Fun things for 2.2:
- e500 virt machine: power off support (needs 3.19 guests) - e500 virt machine: -device eTSEC support - new framework to allow dynamic spawning of sysbus devices - spapr: enable migration of nvram - new 440x5wDFPU cpu type - Altivec and other random fixes
# gpg: Signature made Tue 04 Nov 2014 22:26:39 GMT using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>"
* remotes/agraf/tags/signed-ppc-for-upstream: (34 commits) spapr: Allow dynamic creation of PHB target-ppc: Fix Altivec Round Opcodes target-ppc: Fix vcmpbfp. Unordered Case target-ppc: Fix Altivec Shifts target-ppc: simplify AES emulation e500: Add support for eTSEC in device tree PPC: e500: Support dynamically spawned sysbus devices sysbus: Add new platform bus helper device sysbus: Expose MMIO enumeration helper sysbus: Expose IRQ enumeration helpers sysbus: Make devices spawnable via -device sysbus: Add dynamic sysbus device search hw/ppc/spapr_pci.c: Avoid functions not in glib 2.12 (g_hash_table_iter_*) ppc: do not look at the MMU index to detect PR/HV mode target-ppc: kvm: Fix memory overflow issue about strncat() spapr_nvram: Enable migration PPC: E500: Hook up power off GPIO to GPIO controller PPC: E500: Instantiate MPC8XXX gpio controller on virt machine PPC: Add MPC8XXX gpio controller target-ppc: Fix an invalid free in opcode table handling code. ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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f7087343 |
| 01-Jul-2014 |
Alexander Graf <agraf@suse.de> |
PPC: e500: Support dynamically spawned sysbus devices
For e500 our approach to supporting dynamically spawned sysbus devices is to create a simple bus from the guest's point of view within which we
PPC: e500: Support dynamically spawned sysbus devices
For e500 our approach to supporting dynamically spawned sysbus devices is to create a simple bus from the guest's point of view within which we map those devices dynamically.
We allocate memory regions always within the "platform" hole in address space and map IRQs to predetermined IRQ lines that are reserved for platform device usage.
This maps really nicely into device tree logic, so we can just tell the guest about our virtual simple bus in device tree as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
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b88e77f4 |
| 01-Oct-2014 |
Alexander Graf <agraf@suse.de> |
PPC: E500: Instantiate MPC8XXX gpio controller on virt machine
With the e500 virt machine, we don't have to adhere to the exact hardware layout of an mpc8544ds board. So there we can just add a qori
PPC: E500: Instantiate MPC8XXX gpio controller on virt machine
With the e500 virt machine, we don't have to adhere to the exact hardware layout of an mpc8544ds board. So there we can just add a qoriq compatible GPIO controller into the system that we can add a power off hook to.
Signed-off-by: Alexander Graf <agraf@suse.de>
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