| /qemu/hw/misc/ |
| H A D | stm32l4x5_exti.c | 69 static unsigned valid_mask(unsigned bank) in valid_mask() argument
71 return MAKE_64BIT_MASK(0, irqs_per_bank[bank]); in valid_mask()
74 static unsigned configurable_mask(unsigned bank) in configurable_mask() argument
76 return valid_mask(bank) & ~exti_romask[bank]; in configurable_mask()
83 for (unsigned bank = 0; bank < EXTI_NUM_REGISTER; bank++) { in stm32l4x5_exti_reset_hold() local
84 s->imr[bank] = exti_romask[bank]; in stm32l4x5_exti_reset_hold()
85 s->emr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
86 s->rtsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
87 s->ftsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
88 s->swier[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
[all …]
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| /qemu/hw/intc/ |
| H A D | omap_intc.c | 58 struct omap_intr_handler_bank_s bank[3]; member
73 level = s->bank[j].irqs & ~s->bank[j].mask & in omap_inth_sir_update()
74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update()
78 p = s->bank[j].priority[i]; in omap_inth_sir_update()
95 has_intr |= s->bank[i].irqs & ~s->bank[i].mask & in omap_inth_update()
96 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); in omap_inth_update()
113 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; in omap_set_intr() local
117 rise = ~bank->irqs & (1 << n); in omap_set_intr()
118 if (~bank->sens_edge & (1 << n)) in omap_set_intr()
119 rise &= ~bank->inputs; in omap_set_intr()
[all …]
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| /qemu/hw/ppc/ |
| H A D | ppc4xx_sdram.c | 52 * The 4xx SDRAM controller supports a small number of banks, and each bank
100 error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n", in ppc4xx_sdram_banks()
111 static void sdram_bank_map(Ppc4xxSdramBank *bank) in sdram_bank_map() argument
113 trace_ppc4xx_sdram_map(bank->base, bank->size); in sdram_bank_map()
114 memory_region_init(&bank->container, NULL, "sdram-container", bank->size); in sdram_bank_map()
115 memory_region_add_subregion(&bank->container, 0, &bank->ram); in sdram_bank_map()
116 memory_region_add_subregion(get_system_memory(), bank->base, in sdram_bank_map()
117 &bank->container); in sdram_bank_map()
120 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) in sdram_bank_unmap() argument
122 trace_ppc4xx_sdram_unmap(bank->base, bank->size); in sdram_bank_unmap()
[all …]
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| H A D | ppc440_uc.c | 60 /* single bank */
72 MemoryRegion bank[4]; member
174 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", in ppc4xx_l2sram_init()
176 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", in ppc4xx_l2sram_init()
178 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", in ppc4xx_l2sram_init()
180 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", in ppc4xx_l2sram_init()
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| /qemu/tests/qtest/ |
| H A D | dm163-test.c | 115 const unsigned bank = (uintptr_t) opaque; in test_dm163_bank() local
116 const int width = bank ? 192 : 144; in test_dm163_bank()
123 GPIO_OUT(SELBK, bank); in test_dm163_bank()
126 /* Fill bank with zeroes */ in test_dm163_bank()
131 /* Fill bank with ones, check that we get the previous zeroes */ in test_dm163_bank()
138 /* Pulse one more bit in the bank, check that we get a one */ in test_dm163_bank()
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| /qemu/target/i386/ |
| H A D | helper.c | 367 int bank; member
389 uint64_t *banks = cenv->mce_banks + 4 * params->bank; in do_inject_x86_mce()
421 * reporting is disabled for the bank in do_inject_x86_mce()
426 " bank %d\n", in do_inject_x86_mce()
427 cs->cpu_index, params->bank); in do_inject_x86_mce()
473 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, in cpu_x86_inject_mce() argument
481 .bank = bank, in cpu_x86_inject_mce()
494 if (bank >= bank_num) { in cpu_x86_inject_mce()
495 monitor_printf(mon, "Invalid MCE bank number\n"); in cpu_x86_inject_mce()
512 params.bank = 1; in cpu_x86_inject_mce()
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| /qemu/hw/net/ |
| H A D | smc91c111.c | 50 int bank; member
80 VMSTATE_INT32(bank, smc91c111_state),
362 s->bank = 0; in smc91c111_reset()
433 s->bank = value; in smc91c111_writeb()
438 switch (s->bank) { in smc91c111_writeb()
607 qemu_log_mask(LOG_GUEST_ERROR, "smc91c111_write(bank:%d) Illegal register" in smc91c111_writeb()
609 s->bank, offset, value); in smc91c111_writeb()
618 return s->bank; in smc91c111_readb()
622 switch (s->bank) { in smc91c111_readb()
754 qemu_log_mask(LOG_GUEST_ERROR, "smc91c111_read(bank:%d) Illegal register" in smc91c111_readb()
[all …]
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| /qemu/include/hw/misc/ |
| H A D | iotkit-sysctl.h | 22 * + sysbus MMIO region 0: the system information register bank
23 * + sysbus MMIO region 1: the system control register bank
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| H A D | armv7m_ras.h | 16 * + sysbus MMIO region 0: the register bank
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| H A D | armsse-cpu-pwrctrl.h | 18 * + sysbus MMIO region 0: the register bank
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| H A D | armsse-cpuid.h | 19 * + sysbus MMIO region 0: the system information register bank
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| H A D | iotkit-sysinfo.h | 19 * + sysbus MMIO region 0: the system information register bank
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| H A D | armsse-mhu.h | 18 * + sysbus MMIO region 0: the system information register bank
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| H A D | mps2-fpgaio.h | 18 * + sysbus MMIO region 0: the register bank
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| H A D | mps2-scc.h | 17 * + sysbus MMIO region 0: the register bank
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| /qemu/qapi/ |
| H A D | cxl.json | 119 # @bank-group: Bank group of the memory event location, incorporating
122 # @bank: Bank of the memory event location. A single bank is accessed
139 '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
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| /qemu/target/sh4/ |
| H A D | op_helper.c | 456 int bank, i; in helper_fipr() local
459 bank = (env->sr & FPSCR_FR) ? 16 : 0; in helper_fipr()
464 p = float32_mul(env->fregs[bank + m + i], in helper_fipr()
465 env->fregs[bank + n + i], in helper_fipr()
471 env->fregs[bank + n + 3] = r; in helper_fipr()
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| /qemu/include/hw/ppc/ |
| H A D | ppc4xx.h | 119 Ppc4xxSdramBank bank[4]; member
145 Ppc4xxSdramBank bank[4]; member
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| /qemu/hw/i2c/ |
| H A D | npcm7xx_smbus.c | 660 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_read() local
710 if (bank) { in npcm7xx_smbus_read()
711 /* Bank 1 */ in npcm7xx_smbus_read()
748 /* Bank 0 */ in npcm7xx_smbus_read()
821 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_write() local
877 if (bank) { in npcm7xx_smbus_write()
878 /* Bank 1 */ in npcm7xx_smbus_write()
915 /* Bank 0 */ in npcm7xx_smbus_write()
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| /qemu/include/hw/timer/ |
| H A D | cmsdk-apb-timer.h | 26 * + sysbus MMIO region 0: the register bank
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| H A D | stellaris-gptm.h | 23 * + sysbus MMIO region 0: register bank
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| H A D | sse-timer.h | 20 * + sysbus MMIO region 0: the register bank
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| H A D | cmsdk-apb-dualtimer.h | 20 * + sysbus MMIO region 0: the register bank
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| /qemu/hw/display/ |
| H A D | dm163.c | 88 * On raising dck, sample selbk to get the bank to use, and in dm163_dck_gpio_handler()
89 * sample sin for the bit to enter into the bank shift buffer. in dm163_dck_gpio_handler()
155 * Bank 0 uses 6 bits per led, so a value may be stored accross in dm163_bank0()
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| /qemu/include/hw/ssi/ |
| H A D | npcm_pspi.h | 36 * Each PSPI has a shared bank of registers, and controls up to four chip
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