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/qemu/target/openrisc/
H A Ddisas.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
54 static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \
60 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
61 INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
62 INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
63 INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
64 INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
65 INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
66 INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
[all …]
H A Dtranslate.c14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * You should have received a copy of the GNU Lesser General Public
53 /* If not -1, jmp_pc contains this value and so is a direct jump. */
419 static bool trans_l_add(DisasContext *dc, arg_dab *a) in trans_l_add() argument
421 check_r0_write(dc, a->d); in trans_l_add()
422 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_add()
426 static bool trans_l_addc(DisasContext *dc, arg_dab *a) in trans_l_addc() argument
428 check_r0_write(dc, a->d); in trans_l_addc()
429 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_addc()
433 static bool trans_l_sub(DisasContext *dc, arg_dab *a) in trans_l_sub() argument
[all …]
/qemu/include/qemu/
H A Dint128.h15 static inline Int128 int128_make64(uint64_t a) in int128_make64() argument
17 return a; in int128_make64()
20 static inline Int128 int128_makes64(int64_t a) in int128_makes64() argument
22 return a; in int128_makes64()
30 static inline uint64_t int128_get64(Int128 a) in int128_get64() argument
32 uint64_t r = a; in int128_get64()
33 assert(r == a); in int128_get64()
37 static inline uint64_t int128_getlo(Int128 a) in int128_getlo() argument
39 return a; in int128_getlo()
42 static inline int64_t int128_gethi(Int128 a) in int128_gethi() argument
[all …]
/qemu/target/tricore/
H A Dcsfr.h.inc1 /* A(ll) access permitted
5 A|R|E(offset, register, feature introducing reg)
7 NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
9 A(0xfe00, PCXI, TRICORE_FEATURE_13)
10 A(0xfe08, PC, TRICORE_FEATURE_13)
11 A(0xfe14, SYSCON, TRICORE_FEATURE_13)
17 A(0xfe2c, ICR, TRICORE_FEATURE_13)
18 A(0xfe38, FCX, TRICORE_FEATURE_13)
19 A(0xfe3c, LCX, TRICORE_FEATURE_13)
22 A(0xC000, DPR0_0L, TRICORE_FEATURE_13)
[all …]
/qemu/target/riscv/insn_trans/
H A Dtrans_rvd.c.inc14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
42 static bool trans_fld(DisasContext *ctx, arg_fld *a)
65 addr = get_address(ctx, a->rs1, a->imm);
66 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
72 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
89 addr = get_address(ctx, a->rs1, a->imm);
90 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
94 static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
97 return trans_fld(ctx, a);
[all …]
H A Dtrans_rvzfh.c.inc12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
43 static bool trans_flh(DisasContext *ctx, arg_flh *a)
52 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
53 if (a->imm) {
55 tcg_gen_addi_tl(temp, t0, a->imm);
59 dest = cpu_fpr[a->rd];
67 static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
75 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
76 if (a->imm) {
[all …]
H A Dtrans_rvf.c.inc14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
42 static bool trans_flw(DisasContext *ctx, arg_flw *a)
56 addr = get_address(ctx, a->rs1, a->imm);
57 dest = cpu_fpr[a->rd];
65 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
78 addr = get_address(ctx, a->rs1, a->imm);
79 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
83 static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
86 return trans_flw(ctx, a);
[all …]
H A Dtrans_xthead.c.inc12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
128 arg_th_addsl##SHAMT * a) \
131 return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
141 static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a)
144 return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
149 static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a)
154 return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
158 static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a,
161 TCGv dest = dest_gpr(ctx, a->rd);
[all …]
H A Dtrans_rvi.c.inc14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
21 static bool trans_illegal(DisasContext *ctx, arg_empty *a)
27 static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
30 return trans_illegal(ctx, a);
33 static bool trans_lui(DisasContext *ctx, arg_lui *a)
35 gen_set_gpri(ctx, a->rd, a->imm);
39 static bool trans_lpad(DisasContext *ctx, arg_lpad *a)
64 if (a->label != 0) {
68 tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip);
[all …]
H A Dtrans_rvzfa.c.inc12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
31 static bool trans_fli_s(DisasContext *ctx, arg_fli_s *a)
37 /* Values below are NaN-boxed to avoid a gen_nanbox_s(). */
73 TCGv_i64 dest = dest_fpr(ctx, a->rd);
74 tcg_gen_movi_i64(dest, fli_s_table[a->rs1]);
75 gen_set_fpr_hs(ctx, a->rd, dest);
81 static bool trans_fli_d(DisasContext *ctx, arg_fli_d *a)
122 TCGv_i64 dest = dest_fpr(ctx, a->rd);
123 tcg_gen_movi_i64(dest, fli_d_table[a->rs1]);
[all …]
H A Dtrans_rvk.c.inc13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
50 static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
53 TCGv shamt = tcg_constant_tl(a->shamt);
54 TCGv dest = dest_gpr(ctx, a->rd);
55 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
56 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
59 gen_set_gpr(ctx, a->rd, dest);
63 static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
67 return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
[all …]
/qemu/target/rx/
H A Ddisas.c12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
196 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
198 if (a->dsp > 0) { in trans_MOV_rm()
200 size[a->sz], a->rs, a->dsp << a->sz, a->rd); in trans_MOV_rm()
203 size[a->sz], a->rs, a->rd); in trans_MOV_rm()
209 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
211 if (a->dsp > 0) { in trans_MOV_mr()
213 size[a->sz], a->dsp << a->sz, a->rs, a->rd); in trans_MOV_mr()
216 size[a->sz], a->rs, a->rd); in trans_MOV_mr()
[all …]
H A Dtranslate.c12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
430 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
435 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
440 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
444 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOV_mr()
445 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
452 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) in trans_MOV_ir() argument
454 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
[all …]
/qemu/tests/tcg/s390x/
H A Dvfminmax.c56 …{/* -inf */ "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", …
57 …{/* -Fn */ "T(b)", "T(M(a,b))", "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", …
58 …{/* -0 */ "T(b)", "T(b)", "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", …
59 …{/* +0 */ "T(b)", "T(b)", "T(b)", "T(a)", "T(a)", "T(a)", "T(a)", …
60 …Fn */ "T(b)", "T(b)", "T(b)", "T(b)", "T(M(a,b))", "T(a)", "T(a)", …
61 … "T(b)", "T(b)", "T(b)", "T(b)", "T(b)", "T(a)", "T(a)", "Xi: T…
62 …", "T(b)", "T(b)", "T(b)", "T(b)", "T(b)", "T(a)", "Xi: T(b*)"},
63 …{/* SNaN */ "Xi: T(a*)", "Xi: T(a*)", "Xi: T(a*)", "Xi: T(a*)", "Xi: T(a*)", "Xi: T(a*)", "Xi: T(a…
72 …{/* -inf */ "T(b)", "T(a)", "T(a)", "T(a)", "T(a)", "T(a)", "T(b)", …
73 …{/* -Fn */ "T(b)", "T(M(a,b))", "T(a)", "T(a)", "T(a)", "T(a)", "T(b)", …
[all …]
/qemu/target/avr/
H A Ddisas.c14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * You should have received a copy of the GNU General Public License
104 static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
111 static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
140 INSN(ADD, "r%d, r%d", a->rd, a->rr)
141 INSN(ADC, "r%d, r%d", a->rd, a->rr)
142 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
143 INSN(SUB, "r%d, r%d", a->rd, a->rr)
144 INSN(SUBI, "r%d, %d", a->rd, a->imm)
145 INSN(SBC, "r%d, r%d", a->rd, a->rr)
[all …]
/qemu/target/ppc/translate/
H A Dfixedpoint-impl.c.inc13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
48 static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
54 static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
58 if (!resolve_PLS_D(ctx, &d, a)) {
64 static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
70 static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
89 if (!store && unlikely(a->ra == a->rt)) {
[all …]
/qemu/target/hexagon/
H A Dfma_emu.c11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * You should have received a copy of the GNU General Public License
93 static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) in int128_sub_borrow() argument
95 Int128 ret = int128_sub(a, b); in int128_sub_borrow()
121 static Accum accum_norm_left(Accum a) in accum_norm_left() argument
123 a.exp--; in accum_norm_left()
124 a.mant = int128_lshift(a.mant, 1); in accum_norm_left()
125 a.mant = int128_or(a.mant, int128_make64(a.guard)); in accum_norm_left()
126 a.guard = a.round; in accum_norm_left()
127 a.round = a.sticky; in accum_norm_left()
[all …]
/qemu/target/arm/tcg/
H A Dtranslate-neon.c16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * You should have received a copy of the GNU Lesser General Public
215 static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) in trans_VCMLA() argument
220 if (a->size == MO_16) { in trans_VCMLA()
224 return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, in trans_VCMLA()
227 return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, in trans_VCMLA()
231 static bool trans_VCADD(DisasContext *s, arg_VCADD *a) in trans_VCADD() argument
238 || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) { in trans_VCADD()
244 ((a->vd | a->vn | a->vm) & 0x10)) { in trans_VCADD()
248 if ((a->vn | a->vm | a->vd) & a->q) { in trans_VCADD()
[all …]
H A Dtranslate-a64.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
97 * have a "unprivileged load/store" variant. Those insns access
117 * Therefore we should never get here with a mmu_idx for in get_a64_user_mem_index()
144 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ in set_btype()
233 * mode we do not have a TLB with which to implement this, so we must
236 * Always return a fresh temporary that we can increment independently
251 /* Insert a zero tag into src, with the result at dst. */
267 * For MTE, check a single logical or atomic access. This probes a single
331 * naturally aligned, but it must not cross a 16-byte boundary.
[all …]
H A Dtranslate-sve.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
87 /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype)
141 arg_rr_esz *a, int data) in gen_gvec_fpst_ah_arg_zz() argument
143 return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data, in gen_gvec_fpst_ah_arg_zz()
144 select_ah_fpst(s, a->esz)); in gen_gvec_fpst_ah_arg_zz()
165 arg_rrr_esz *a, int data) in gen_gvec_ool_arg_zzz() argument
167 return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data); in gen_gvec_ool_arg_zzz()
191 arg_rrr_esz *a, int data) in gen_gvec_fpst_arg_zzz() argument
193 return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data, in gen_gvec_fpst_arg_zzz()
[all …]
H A Dtranslate-mve.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
50 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
85 * This is a beatwise insn: check that ECI is valid (not a in mve_eci_check()
118 * For insns which don't call a helper function that will call in mve_update_and_store_eci()
144 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, in do_ldst() argument
152 !mve_check_qreg_bank(s, a->qd) || in do_ldst()
158 if (a->rn == 15 || (a->rn == 13 && a->w)) { in do_ldst()
166 offset = a->imm << msize; in do_ldst()
167 if (!a->a) { in do_ldst()
[all …]
H A Darith_helper.c24 static inline uint16_t add16_sat(uint16_t a, uint16_t b) in add16_sat() argument
28 res = a + b; in add16_sat()
29 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { in add16_sat()
30 if (a & 0x8000) { in add16_sat()
40 static inline uint8_t add8_sat(uint8_t a, uint8_t b) in add8_sat() argument
44 res = a + b; in add8_sat()
45 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { in add8_sat()
46 if (a & 0x80) { in add8_sat()
56 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) in sub16_sat() argument
60 res = a - b; in sub16_sat()
[all …]
/qemu/fpu/
H A Dsoftfloat.c4 * The code in this source file is derived from release 2a of the SoftFloat
9 * the SoftFloat-2a license
14 * taken to be licensed under the Softfloat-2a license unless specifically
21 Arithmetic Package, Release 2a.
27 of this code was written as part of a project to build a fixed-point vector
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
102 * exception flags is not trivial: reading the host's flags register with a
106 * We address these challenges by leveraging the host FPU for a subset of the
109 * Guo, Yu-Chuan, et al. "Translating the ARM Neon and VFP instructions in a
123 * denormal/inf/NaN; (2) when operands are not guaranteed to lead to a 0 result
[all …]
/qemu/tests/qemu-iotests/
H A D059.out2062 … use relative paths with VMDK descriptor file $QUORUM_FILE: Cannot generate a base directory for q…
2277 e100000000: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2278 e100000010: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2279 e100000020: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2280 e100000030: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2281 e100000040: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2282 e100000050: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2283 e100000060: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2284 e100000070: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2285 e100000080: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
[all …]
/qemu/target/mips/tcg/
H A Dtx79_translate.c65 static bool trans_MFHI1(DisasContext *ctx, arg_r *a) in trans_MFHI1() argument
67 gen_store_gpr(cpu_HI[1], a->rd); in trans_MFHI1()
72 static bool trans_MFLO1(DisasContext *ctx, arg_r *a) in trans_MFLO1() argument
74 gen_store_gpr(cpu_LO[1], a->rd); in trans_MFLO1()
79 static bool trans_MTHI1(DisasContext *ctx, arg_r *a) in trans_MTHI1() argument
81 gen_load_gpr(cpu_HI[1], a->rs); in trans_MTHI1()
86 static bool trans_MTLO1(DisasContext *ctx, arg_r *a) in trans_MTLO1() argument
88 gen_load_gpr(cpu_LO[1], a->rs); in trans_MTLO1()
117 static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, in trans_parallel_arith() argument
122 if (a->rd == 0) { in trans_parallel_arith()
[all …]

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