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/linux-6.15/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
21 Description: (Read) Shows the value held by the TMC status register. The value
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
28 Description: (Read) Shows the value held by the TMC RAM Read Pointer register
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
37 Description: (Read) Shows the value held by the TMC RAM Write Pointer register
42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
49 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
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/linux-6.15/include/trace/events/
Dtimer_migration.h65 TP_PROTO(struct tmigr_cpu *tmc),
67 TP_ARGS(tmc),
79 __entry->parent = tmc->tmgroup;
80 __entry->cpu = tmc->cpuevt.cpu;
81 __entry->lvl = tmc->tmgroup->level;
82 __entry->numa_node = tmc->tmgroup->numa_node;
83 __entry->num_children = tmc->tmgroup->num_children;
84 __entry->groupmask = tmc->groupmask;
142 TP_PROTO(struct tmigr_cpu *tmc),
144 TP_ARGS(tmc),
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/linux-6.15/kernel/time/
Dtimer_migration.c428 static inline bool tmigr_is_not_available(struct tmigr_cpu *tmc) in tmigr_is_not_available() argument
430 return !(tmc->tmgroup && tmc->online); in tmigr_is_not_available()
526 struct tmigr_cpu *tmc) in __walk_groups() argument
528 struct tmigr_group *child = NULL, *group = tmc->tmgroup; in __walk_groups()
547 static void walk_groups(up_f up, struct tmigr_walk *data, struct tmigr_cpu *tmc) in walk_groups() argument
549 lockdep_assert_held(&tmc->lock); in walk_groups()
551 __walk_groups(up, data, tmc); in walk_groups()
673 static void __tmigr_cpu_activate(struct tmigr_cpu *tmc) in __tmigr_cpu_activate() argument
677 data.childmask = tmc->groupmask; in __tmigr_cpu_activate()
679 trace_tmigr_cpu_active(tmc); in __tmigr_cpu_activate()
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/linux-6.15/drivers/scsi/
Dfdomain.c3 * Driver for Future Domain TMC-16x0 and TMC-3260 SCSI host adapters
12 * TMC-1800, TMC-18C50, TMC-18C30, TMC-36C70
14 * Future Domain TMC-1650, TMC-1660, TMC-1670, TMC-1680, TMC-1610M/MER/MEX
15 * Future Domain TMC-3260 (PCI)
30 * If you have a TMC-8xx or TMC-9xx board, then this is not the driver for
35 * This is the Linux low-level SCSI driver for Future Domain TMC-1660/1680
36 * TMC-1650/1670, and TMC-3260 SCSI host adapters. The 1650 and 1670 have a
39 * controllers built in. The TMC-3260 is a PCI bus card.
41 * Future Domain's older boards are based on the TMC-1800 chip, and this
42 * driver was originally written for a TMC-1680 board with the TMC-1800 chip.
[all …]
Dfdomain_isa.c35 /* This driver works *ONLY* for Future Domain cards using the TMC-1800,
36 * TMC-18C50, or TMC-18C30 chip. This includes models TMC-1650, 1660, 1670,
41 * work with this driver (these TMC-8xx and TMC-9xx boards may work with the
74 { "FUTURE DOMAIN TMC-18XX (C) 1993 V3.203/12/93", 5, 44, 7, 0 },
218 MODULE_DESCRIPTION("Future Domain TMC-16x0 ISA SCSI driver");
Dfdomain_pci.c67 MODULE_DESCRIPTION("Future Domain TMC-3260 PCI SCSI driver");
/linux-6.15/drivers/hwtracing/coresight/
Dcoresight-tmc.h56 * TMC AXICTL format for SoC-400
63 * TMC AXICTL format for SoC-600, as above except:
123 /* TMC ETR Capability bit definitions */
129 * retained when TMC leaves Disabled state, allowing us to continue
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
141 /* TMC metadata region for ETR and ETF configurations */
162 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
176 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
212 * struct tmc_drvdata - specifics associated to an TMC component
216 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
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DMakefile30 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
31 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
32 coresight-tmc-etr.o
Dcoresight-tmc-core.c32 #include "coresight-tmc.h"
46 "timeout while waiting for TMC to be Ready\n"); in tmc_wait_for_tmcready()
125 "Data invalid in tmc crash metadata\n"); in is_tmc_crashdata_valid()
143 "CRC mismatch in tmc crash metadata\n"); in is_tmc_crashdata_valid()
149 "CRC mismatch in tmc crash tracedata\n"); in is_tmc_crashdata_valid()
211 "Offset and length invalid in tmc crash metadata\n"); in tmc_prepare_crashdata()
247 dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); in tmc_read_prepare()
269 dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); in tmc_read_unprepare()
519 /* Only permitted for TMC-ETRs */ in buffer_size_store()
609 * this property is only checked for Coresight SoC 400 TMC configured in tmc_etr_can_use_sg()
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Dcoresight-tmc-etf.c13 #include "coresight-tmc.h"
30 "Failed to enable: TMC not ready\n"); in __tmc_etb_enable_hw()
93 * read before the TMC is disabled. in __tmc_etb_disable_hw()
118 "Failed to enable : TMC is not ready\n"); in __tmc_etf_enable_hw()
327 dev_dbg(&csdev->dev, "TMC-ETB/ETF enabled\n"); in tmc_enable_etf_sink()
358 dev_dbg(&csdev->dev, "TMC-ETB/ETF disabled\n"); in tmc_disable_etf_sink()
389 dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); in tmc_enable_etf_link()
416 dev_dbg(&csdev->dev, "TMC-ETF disabled\n"); in tmc_disable_etf_link()
519 * The TMC RAM buffer may be bigger than the space available in the in tmc_update_etf_buffer()
727 /* Disable the TMC if need be */ in tmc_read_prepare_etb()
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DKconfig35 tristate "Coresight generic TMC driver"
46 module will be called coresight-tmc.
54 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
137 tristate "CoreSight TMC Control Unit driver"
140 This driver provides support for CoreSight TMC Control Unit
142 primarily used for controlling the behaviors of the TMC
Dcoresight-tmc-etr.c20 #include "coresight-tmc.h"
63 * The TMC ETR SG has a page size of 4K. The SG table contains pointers
110 * @hwaddr: hwaddress used by the TMC, which is the base
123 * Each TMC page can map (ETR_SG_PTRS_PER_PAGE - 1) buffer pointers,
316 * tmc_alloc_sg_table: Allocate and setup dma pages for the TMC SG table
317 * and data buffers. TMC writes to the data buffers and reads from the SG
561 * tmc_init_etr_sg_table: Allocate a TMC ETR SG table, data buffer of @size and
564 * @dev - Device pointer for the TMC
591 /* TMC should use table base address for DBA */ in tmc_init_etr_sg_table()
847 * TMC ETR could be connected to a CATU device, which can provide address
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Dcoresight-ctcu-core.c28 * The TMC Coresight Control Unit utilizes four ATID registers to control the data
29 * filter function based on the trace ID for each TMC ETR sink. The length of each
89 * @port_num: port number connected to TMC ETR sink.
326 MODULE_DESCRIPTION("CoreSight TMC Control Unit driver");
/linux-6.15/Documentation/devicetree/bindings/arm/
Darm,coresight-tmc.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
32 const: arm,coresight-tmc
42 - const: arm,coresight-tmc
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
75 Indicates that the TMC-ETR can safely use the SG mode on this system.
79 The maximum burst size initiated by TMC on the AXI master interface. The
139 compatible = "arm,coresight-tmc", "arm,primecell";
Dqcom,coresight-ctcu.yaml7 title: CoreSight TMC Control Unit
15 The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
20 The Coresight TMC Control unit controls various Coresight behaviors.
21 It works as a helper device when connected to TMC ETR device.
23 the source device's Trace ID for TMC ETR device. The trace data with
Dqcom,coresight-remote-etm.yaml17 via coresight TMC sinks.
/linux-6.15/Documentation/ABI/stable/
Dsysfs-driver-usb-usbtmc6 These files show the various USB TMC capabilities as described
8 can be found in the USB TMC documents from the USB-IF entitled
20 These files show the various USB TMC capabilities as described
22 can be found in the USB TMC documents from the USB-IF entitled
/linux-6.15/drivers/net/wan/
Dhd64572.c362 unsigned int tmc, br = 10, brv = 1024; in sca_set_port() local
370 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ in sca_set_port()
371 tmc = CLOCK_BASE / brv / port->settings.clock_rate; in sca_set_port()
372 } while (br > 1 && tmc <= 128); in sca_set_port()
374 if (tmc < 1) { in sca_set_port()
375 tmc = 1; in sca_set_port()
376 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ in sca_set_port()
378 } else if (tmc > 255) { in sca_set_port()
379 tmc = 256; /* tmc=0 means 256 - low baud rates */ in sca_set_port()
382 port->settings.clock_rate = CLOCK_BASE / brv / tmc; in sca_set_port()
[all …]
Dhd64570.c406 unsigned int tmc, br = 10, brv = 1024; in sca_set_port() local
414 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ in sca_set_port()
415 tmc = CLOCK_BASE / brv / port->settings.clock_rate; in sca_set_port()
416 } while (br > 1 && tmc <= 128); in sca_set_port()
418 if (tmc < 1) { in sca_set_port()
419 tmc = 1; in sca_set_port()
420 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ in sca_set_port()
422 } else if (tmc > 255) { in sca_set_port()
423 tmc = 256; /* tmc=0 means 256 - low baud rates */ in sca_set_port()
426 port->settings.clock_rate = CLOCK_BASE / brv / tmc; in sca_set_port()
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/linux-6.15/Documentation/admin-guide/media/
Dci.rst35 eg: $ szap -c channels.conf -r "TMC" -x
39 eg: TMC:11996:h:0:27500:278:512:650:321
47 eg: $ ca_zap channels.conf "TMC"
Dsi470x.rst36 - Si4706: Enhanced FM RDS/TMC radio receiver, no external antenna required, RDS
85 There is currently no project for making TMC sentences human readable.
/linux-6.15/arch/arm64/boot/dts/hisilicon/
Dhi3660-coresight.dtsi136 compatible = "arm,coresight-tmc", "arm,primecell";
282 compatible = "arm,coresight-tmc", "arm,primecell";
374 compatible = "arm,coresight-tmc", "arm,primecell";
433 compatible = "arm,coresight-tmc", "arm,primecell";
Dhi6220-coresight.dtsi39 compatible = "arm,coresight-tmc", "arm,primecell";
100 compatible = "arm,coresight-tmc", "arm,primecell";
369 /* CTI 0 - TMC and TPIU connections */
/linux-6.15/include/uapi/linux/usb/
Dtmc.h22 /* USB TMC status values */
30 /* USB TMC requests values */
/linux-6.15/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi212 compatible = "arm,coresight-tmc", "arm,primecell";
277 compatible = "arm,coresight-tmc", "arm,primecell";
302 compatible = "arm,coresight-tmc", "arm,primecell";

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