1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright(C) 2015 Linaro Limited. All rights reserved.
4  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5  */
6 
7 #ifndef _CORESIGHT_TMC_H
8 #define _CORESIGHT_TMC_H
9 
10 #include <linux/dma-mapping.h>
11 #include <linux/idr.h>
12 #include <linux/miscdevice.h>
13 #include <linux/mutex.h>
14 #include <linux/refcount.h>
15 #include <linux/crc32.h>
16 
17 #define TMC_RSZ			0x004
18 #define TMC_STS			0x00c
19 #define TMC_RRD			0x010
20 #define TMC_RRP			0x014
21 #define TMC_RWP			0x018
22 #define TMC_TRG			0x01c
23 #define TMC_CTL			0x020
24 #define TMC_RWD			0x024
25 #define TMC_MODE		0x028
26 #define TMC_LBUFLEVEL		0x02c
27 #define TMC_CBUFLEVEL		0x030
28 #define TMC_BUFWM		0x034
29 #define TMC_RRPHI		0x038
30 #define TMC_RWPHI		0x03c
31 #define TMC_AXICTL		0x110
32 #define TMC_DBALO		0x118
33 #define TMC_DBAHI		0x11c
34 #define TMC_FFSR		0x300
35 #define TMC_FFCR		0x304
36 #define TMC_PSCR		0x308
37 #define TMC_ITMISCOP0		0xee0
38 #define TMC_ITTRFLIN		0xee8
39 #define TMC_ITATBDATA0		0xeec
40 #define TMC_ITATBCTR2		0xef0
41 #define TMC_ITATBCTR1		0xef4
42 #define TMC_ITATBCTR0		0xef8
43 #define TMC_AUTHSTATUS		0xfb8
44 
45 /* register description */
46 /* TMC_CTL - 0x020 */
47 #define TMC_CTL_CAPT_EN		BIT(0)
48 /* TMC_STS - 0x00C */
49 #define TMC_STS_TMCREADY_BIT	2
50 #define TMC_STS_FULL		BIT(0)
51 #define TMC_STS_TRIGGERED	BIT(1)
52 #define TMC_STS_MEMERR		BIT(5)
53 /*
54  * TMC_AXICTL - 0x110
55  *
56  * TMC AXICTL format for SoC-400
57  *	Bits [0-1]	: ProtCtrlBit0-1
58  *	Bits [2-5]	: CacheCtrlBits 0-3 (AXCACHE)
59  *	Bit  6		: Reserved
60  *	Bit  7		: ScatterGatherMode
61  *	Bits [8-11]	: WrBurstLen
62  *	Bits [12-31]	: Reserved.
63  * TMC AXICTL format for SoC-600, as above except:
64  *	Bits [2-5]	: AXI WCACHE
65  *	Bits [16-19]	: AXI RCACHE
66  *	Bits [20-31]	: Reserved
67  */
68 #define TMC_AXICTL_CLEAR_MASK 0xfbf
69 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
70 
71 #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
72 #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
73 #define TMC_AXICTL_SCT_GAT_MODE	BIT(7)
74 #define TMC_AXICTL_WR_BURST(v)	(((v) & 0xf) << 8)
75 #define TMC_AXICTL_WR_BURST_16	0xf
76 /* Write-back Read and Write-allocate */
77 #define TMC_AXICTL_AXCACHE_OS	(0xf << 2)
78 #define TMC_AXICTL_ARCACHE_OS	(0xf << 16)
79 
80 /* TMC_FFSR - 0x300 */
81 #define TMC_FFSR_FT_STOPPED	BIT(1)
82 
83 /* TMC_FFCR - 0x304 */
84 #define TMC_FFCR_FLUSHMAN_BIT	6
85 #define TMC_FFCR_EN_FMT		BIT(0)
86 #define TMC_FFCR_EN_TI		BIT(1)
87 #define TMC_FFCR_FON_FLIN	BIT(4)
88 #define TMC_FFCR_FON_TRIG_EVT	BIT(5)
89 #define TMC_FFCR_TRIGON_TRIGIN	BIT(8)
90 #define TMC_FFCR_STOP_ON_FLUSH	BIT(12)
91 
92 
93 #define TMC_DEVID_NOSCAT	BIT(24)
94 
95 #define TMC_DEVID_AXIAW_VALID	BIT(16)
96 #define TMC_DEVID_AXIAW_SHIFT	17
97 #define TMC_DEVID_AXIAW_MASK	0x7f
98 
99 #define TMC_AUTH_NSID_MASK	GENMASK(1, 0)
100 
101 /* Major version 1 Minor version 0 */
102 #define CS_CRASHDATA_VERSION	(1 << 16)
103 
104 enum tmc_config_type {
105 	TMC_CONFIG_TYPE_ETB,
106 	TMC_CONFIG_TYPE_ETR,
107 	TMC_CONFIG_TYPE_ETF,
108 };
109 
110 enum tmc_mode {
111 	TMC_MODE_CIRCULAR_BUFFER,
112 	TMC_MODE_SOFTWARE_FIFO,
113 	TMC_MODE_HARDWARE_FIFO,
114 };
115 
116 enum tmc_mem_intf_width {
117 	TMC_MEM_INTF_WIDTH_32BITS	= 1,
118 	TMC_MEM_INTF_WIDTH_64BITS	= 2,
119 	TMC_MEM_INTF_WIDTH_128BITS	= 4,
120 	TMC_MEM_INTF_WIDTH_256BITS	= 8,
121 };
122 
123 /* TMC ETR Capability bit definitions */
124 #define TMC_ETR_SG			(0x1U << 0)
125 /* ETR has separate read/write cache encodings */
126 #define TMC_ETR_AXI_ARCACHE		(0x1U << 1)
127 /*
128  * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
129  * retained when TMC leaves Disabled state, allowing us to continue
130  * the tracing from a point where we stopped. This also implies that
131  * the RRP/RWP/STS.Full should always be programmed to the correct
132  * value. Unfortunately this is not advertised by the hardware,
133  * so we have to rely on PID of the IP to detect the functionality.
134  */
135 #define TMC_ETR_SAVE_RESTORE		(0x1U << 2)
136 
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
138 #define CORESIGHT_SOC_600_ETR_CAPS	\
139 	(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
140 
141 /* TMC metadata region for ETR and ETF configurations */
142 struct tmc_crash_metadata {
143 	uint32_t crc32_mdata;	/* crc of metadata */
144 	uint32_t crc32_tdata;	/* crc of tracedata */
145 	uint32_t version;	/* 31:16 Major version, 15:0 Minor version */
146 	uint32_t valid;         /* Indicate if this ETF/ETR was enabled */
147 	uint32_t tmc_ram_size;  /* Ram Size register */
148 	uint32_t tmc_sts;       /* Status register */
149 	uint32_t tmc_mode;	/* Mode register */
150 	uint32_t tmc_ffcr;	/* Formatter and flush control register */
151 	uint32_t tmc_ffsr;	/* Formatter and flush status register */
152 	uint32_t reserved32;
153 	uint64_t tmc_rrp;       /* Ram Read pointer register */
154 	uint64_t tmc_rwp;       /* Ram Write pointer register */
155 	uint64_t tmc_dba;	/* Data buffer address register */
156 	uint64_t trace_paddr;	/* Phys address of trace buffer */
157 	uint64_t reserved64[3];
158 };
159 
160 enum etr_mode {
161 	ETR_MODE_FLAT,		/* Uses contiguous flat buffer */
162 	ETR_MODE_ETR_SG,	/* Uses in-built TMC ETR SG mechanism */
163 	ETR_MODE_CATU,		/* Use SG mechanism in CATU */
164 	ETR_MODE_RESRV,		/* Use reserved region contiguous buffer */
165 	ETR_MODE_AUTO,		/* Use the default mechanism */
166 };
167 
168 struct etr_buf_operations;
169 
170 /**
171  * struct etr_buf - Details of the buffer used by ETR
172  * refcount	; Number of sources currently using this etr_buf.
173  * @mode	: Mode of the ETR buffer, contiguous, Scatter Gather etc.
174  * @full	: Trace data overflow
175  * @size	: Size of the buffer.
176  * @hwaddr	: Address to be programmed in the TMC:DBA{LO,HI}
177  * @offset	: Offset of the trace data in the buffer for consumption.
178  * @len		: Available trace data @buf (may round up to the beginning).
179  * @ops		: ETR buffer operations for the mode.
180  * @private	: Backend specific information for the buf
181  */
182 struct etr_buf {
183 	refcount_t			refcount;
184 	enum etr_mode			mode;
185 	bool				full;
186 	ssize_t				size;
187 	dma_addr_t			hwaddr;
188 	unsigned long			offset;
189 	s64				len;
190 	const struct etr_buf_operations	*ops;
191 	void				*private;
192 };
193 
194 /**
195  * @paddr	: Start address of reserved memory region.
196  * @vaddr	: Corresponding CPU virtual address.
197  * @size	: Size of reserved memory region.
198  * @offset	: Offset of the trace data in the buffer for consumption.
199  * @reading	: Flag to indicate if reading is active
200  * @len	: Available trace data @buf (may round up to the beginning).
201  */
202 struct tmc_resrv_buf {
203 	phys_addr_t     paddr;
204 	void		*vaddr;
205 	size_t		size;
206 	unsigned long	offset;
207 	bool		reading;
208 	s64		len;
209 };
210 
211 /**
212  * struct tmc_drvdata - specifics associated to an TMC component
213  * @pclk:	APB clock if present, otherwise NULL
214  * @base:	memory mapped base address for this component.
215  * @csdev:	component vitals needed by the framework.
216  * @miscdev:	specifics to handle "/dev/xyz.tmc" entry.
217  * @crashdev:	specifics to handle "/dev/crash_tmc_xyz" entry for reading
218  *		crash tracedata.
219  * @spinlock:	only one at a time pls.
220  * @pid:	Process ID of the process that owns the session that is using
221  *		this component. For example this would be the pid of the Perf
222  *		process.
223  * @stop_on_flush: Stop on flush trigger user configuration.
224  * @buf:	Snapshot of the trace data for ETF/ETB.
225  * @etr_buf:	details of buffer used in TMC-ETR
226  * @len:	size of the available trace for ETF/ETB.
227  * @size:	trace buffer size for this TMC (common for all modes).
228  * @max_burst_size: The maximum burst size that can be initiated by
229  *		TMC-ETR on AXI bus.
230  * @config_type: TMC variant, must be of type @tmc_config_type.
231  * @memwidth:	width of the memory interface databus, in bytes.
232  * @trigger_cntr: amount of words to store after a trigger.
233  * @etr_caps:	Bitmask of capabilities of the TMC ETR, inferred from the
234  *		device configuration register (DEVID)
235  * @idr:	Holds etr_bufs allocated for this ETR.
236  * @idr_mutex:	Access serialisation for idr.
237  * @sysfs_buf:	SYSFS buffer for ETR.
238  * @perf_buf:	PERF buffer for ETR.
239  * @resrv_buf:  Used by ETR as hardware trace buffer and for trace data
240  *		retention (after crash) only when ETR_MODE_RESRV buffer
241  *		mode is enabled. Used by ETF for trace data retention
242  *		(after crash) by default.
243  * @crash_mdata: Reserved memory for storing tmc crash metadata.
244  *		 Used by ETR/ETF.
245  */
246 struct tmc_drvdata {
247 	struct clk		*pclk;
248 	void __iomem		*base;
249 	struct coresight_device	*csdev;
250 	struct miscdevice	miscdev;
251 	struct miscdevice	crashdev;
252 	raw_spinlock_t		spinlock;
253 	pid_t			pid;
254 	bool			reading;
255 	bool			stop_on_flush;
256 	union {
257 		char		*buf;		/* TMC ETB */
258 		struct etr_buf	*etr_buf;	/* TMC ETR */
259 	};
260 	u32			len;
261 	u32			size;
262 	u32			max_burst_size;
263 	enum tmc_config_type	config_type;
264 	enum tmc_mem_intf_width	memwidth;
265 	u32			trigger_cntr;
266 	u32			etr_caps;
267 	enum etr_mode		etr_mode;
268 	struct idr		idr;
269 	struct mutex		idr_mutex;
270 	struct etr_buf		*sysfs_buf;
271 	struct etr_buf		*perf_buf;
272 	struct tmc_resrv_buf	resrv_buf;
273 	struct tmc_resrv_buf	crash_mdata;
274 };
275 
276 struct etr_buf_operations {
277 	int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
278 		     int node, void **pages);
279 	void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
280 	ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
281 			    char **bufpp);
282 	void (*free)(struct etr_buf *etr_buf);
283 };
284 
285 /**
286  * struct tmc_pages - Collection of pages used for SG.
287  * @nr_pages:		Number of pages in the list.
288  * @daddrs:		Array of DMA'able page address.
289  * @pages:		Array pages for the buffer.
290  */
291 struct tmc_pages {
292 	int nr_pages;
293 	dma_addr_t	*daddrs;
294 	struct page	**pages;
295 };
296 
297 /*
298  * struct tmc_sg_table - Generic SG table for TMC
299  * @dev:		Device for DMA allocations
300  * @table_vaddr:	Contiguous Virtual address for PageTable
301  * @data_vaddr:		Contiguous Virtual address for Data Buffer
302  * @table_daddr:	DMA address of the PageTable base
303  * @node:		Node for Page allocations
304  * @table_pages:	List of pages & dma address for Table
305  * @data_pages:		List of pages & dma address for Data
306  */
307 struct tmc_sg_table {
308 	struct device *dev;
309 	void *table_vaddr;
310 	void *data_vaddr;
311 	dma_addr_t table_daddr;
312 	int node;
313 	struct tmc_pages table_pages;
314 	struct tmc_pages data_pages;
315 };
316 
317 /* Generic functions */
318 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
319 void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
320 void tmc_enable_hw(struct tmc_drvdata *drvdata);
321 void tmc_disable_hw(struct tmc_drvdata *drvdata);
322 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
323 int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata);
324 
325 /* ETB/ETF functions */
326 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
327 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
328 extern const struct coresight_ops tmc_etb_cs_ops;
329 extern const struct coresight_ops tmc_etf_cs_ops;
330 
331 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
332 				loff_t pos, size_t len, char **bufpp);
333 /* ETR functions */
334 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
335 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
336 void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
337 extern const struct coresight_ops tmc_etr_cs_ops;
338 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
339 				loff_t pos, size_t len, char **bufpp);
340 
341 
342 #define TMC_REG_PAIR(name, lo_off, hi_off)				\
343 static inline u64							\
344 tmc_read_##name(struct tmc_drvdata *drvdata)				\
345 {									\
346 	return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
347 }									\
348 static inline void							\
349 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val)			\
350 {									\
351 	csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
352 }
353 
TMC_REG_PAIR(rrp,TMC_RRP,TMC_RRPHI)354 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
355 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
356 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
357 
358 /* Initialise the caps from unadvertised static capabilities of the device */
359 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
360 {
361 	WARN_ON(drvdata->etr_caps);
362 	drvdata->etr_caps = dev_caps;
363 }
364 
tmc_etr_set_cap(struct tmc_drvdata * drvdata,u32 cap)365 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
366 {
367 	drvdata->etr_caps |= cap;
368 }
369 
tmc_etr_has_cap(struct tmc_drvdata * drvdata,u32 cap)370 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
371 {
372 	return !!(drvdata->etr_caps & cap);
373 }
374 
375 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,
376 					int node,
377 					int nr_tpages,
378 					int nr_dpages,
379 					void **pages);
380 void tmc_free_sg_table(struct tmc_sg_table *sg_table);
381 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table);
382 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
383 				  u64 offset, u64 size);
384 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,
385 			      u64 offset, size_t len, char **bufpp);
386 
387 static inline unsigned long
tmc_sg_table_buf_size(struct tmc_sg_table * sg_table)388 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
389 {
390 	return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;
391 }
392 
tmc_has_reserved_buffer(struct tmc_drvdata * drvdata)393 static inline bool tmc_has_reserved_buffer(struct tmc_drvdata *drvdata)
394 {
395 	if (drvdata->resrv_buf.vaddr &&
396 	    drvdata->resrv_buf.size)
397 		return true;
398 	return false;
399 }
400 
tmc_has_crash_mdata_buffer(struct tmc_drvdata * drvdata)401 static inline bool tmc_has_crash_mdata_buffer(struct tmc_drvdata *drvdata)
402 {
403 	if (drvdata->crash_mdata.vaddr &&
404 	    drvdata->crash_mdata.size)
405 		return true;
406 	return false;
407 }
408 
tmc_crashdata_set_invalid(struct tmc_drvdata * drvdata)409 static inline void tmc_crashdata_set_invalid(struct tmc_drvdata *drvdata)
410 {
411 	struct tmc_crash_metadata *mdata;
412 
413 	mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
414 
415 	if (tmc_has_crash_mdata_buffer(drvdata))
416 		mdata->valid = false;
417 }
418 
find_crash_metadata_crc(struct tmc_crash_metadata * md)419 static inline uint32_t find_crash_metadata_crc(struct tmc_crash_metadata *md)
420 {
421 	unsigned long crc_size;
422 
423 	crc_size = sizeof(struct tmc_crash_metadata) -
424 		offsetof(struct tmc_crash_metadata, crc32_tdata);
425 	return crc32_le(0, (void *)&md->crc32_tdata, crc_size);
426 }
427 
find_crash_tracedata_crc(struct tmc_drvdata * drvdata,struct tmc_crash_metadata * md)428 static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata,
429 						struct tmc_crash_metadata *md)
430 {
431 	unsigned long crc_size;
432 
433 	/* Take CRC of configured buffer size to keep it simple */
434 	crc_size = md->tmc_ram_size << 2;
435 	return crc32_le(0, (void *)drvdata->resrv_buf.vaddr, crc_size);
436 }
437 
438 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
439 
440 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
441 void tmc_etr_remove_catu_ops(void);
442 struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
443 				   enum cs_mode mode, void *data);
444 extern const struct attribute_group coresight_etr_group;
445 
446 #endif
447