Home
last modified time | relevance | path

Searched full:svade (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/riscv/
Dextensions.yaml174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
180 Both Svade and Svadu extensions control the hardware behavior when
183 1) Neither Svade nor Svadu present in DT => It is technically
184 unknown whether the platform uses Svade or Svadu. Supervisor
187 2) Only Svade present in DT => Supervisor must assume Svade to be
191 4) Both Svade and Svadu present in DT => Supervisor must assume
199 privileged ISA specification. Please refer to Svade dt-binding
/linux-6.15/arch/riscv/kernel/
Dcpufeature.c254 /* SVADE has already been detected, use SVADE only */ in riscv_ext_svadu_validate()
520 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
/linux-6.15/tools/testing/selftests/kvm/riscv/
Dget-reg-list.c433 KVM_ISA_EXT_ARR(SVADE), in isa_ext_single_id_to_str()
975 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
/linux-6.15/arch/riscv/kvm/
Dvcpu_onereg.c44 KVM_ISA_EXT_ARR(SVADE),
210 * Svade can't be disabled unless we support Svadu. in kvm_riscv_vcpu_isa_disable_allowed()
Dvcpu.c562 !riscv_isa_extension_available(isa, SVADE)) in kvm_riscv_vcpu_setup_config()
/linux-6.15/arch/riscv/include/asm/
Dpgtable.h671 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By