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/qemu/hw/i2c/
H A DKconfig9 config SMBUS config
15 select SMBUS
23 select SMBUS
47 select SMBUS
H A Dpm_smbus.c2 * PC SMBus implementation
74 I2CBus *bus = s->smbus; in smb_transaction()
134 s->smb_blkdata = i2c_recv(s->smbus); in smb_transaction()
280 ret = smbus_write_block(s->smbus, smb_addr, cmd, s->smb_data, in smb_ioport_writeb()
296 s->smb_blkdata = i2c_recv(s->smbus); in smb_ioport_writeb()
297 i2c_nack(s->smbus); in smb_ioport_writeb()
298 i2c_end_transfer(s->smbus); in smb_ioport_writeb()
307 s->smb_blkdata = i2c_recv(s->smbus); in smb_ioport_writeb()
323 i2c_end_transfer(s->smbus); in smb_ioport_writeb()
480 smb->smbus = i2c_init_bus(parent, "i2c"); in pm_smbus_init()
[all …]
H A Dsmbus_slave.c2 * QEMU SMBus device emulation.
4 * This code is a helper for SMBus device emulation. It implements an
5 * I2C device interface and runs the SMBus protocol from the device
26 do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
29 fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
35 fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
H A Dsmbus_eeprom.c2 * QEMU SMBus EEPROM device
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
99 .name = "smbus-eeprom",
165 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) in DEFINE_TYPES()
173 qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal); in DEFINE_TYPES()
176 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, in smbus_eeprom_init() argument
189 smbus_eeprom_init_one(smbus, 0x50 + i, in smbus_eeprom_init()
H A Dsmbus_master.c2 * QEMU SMBus host (master) emulation.
4 * This code emulates SMBus transactions from the master point of view,
5 * it runs the individual I2C transaction to do the SMBus protocol
H A Dsmbus_ich9.c116 BusState *bus = BUS(s->smb.smbus); in build_ich9_smb_aml()
132 dc->desc = "ICH9 SMBUS Bridge"; in ich9_smb_class_init()
H A Dcore.c114 * This corresponds with the way real hardware works. The SMBus
140 * This happens with any SMBus transaction, even on a pure I2C in i2c_do_start_transfer()
/qemu/include/hw/i2c/
H A Dnpcm7xx_smbus.h2 * Nuvoton NPCM7xx SMBus Module.
56 * @addr: The SMBus module's own addresses on the I2C bus.
63 * @t_out: The SMBus timeout register.
69 * @status: The current status of the SMBus.
109 #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
H A Dsmbus_slave.h2 * QEMU SMBus device (slave) API
31 #define TYPE_SMBUS_DEVICE "smbus-device"
40 * An operation with no data, special in SMBus.
70 /* The SMBus protocol is implemented on top of I2C. */
91 * SMBus slave data needs to be transferred.
H A Dpm_smbus.h10 I2CBus *smbus; member
H A Dsmbus_eeprom.h2 * QEMU SMBus EEPROM API
H A Dsmbus_master.h2 * QEMU SMBus host (master) API
/qemu/hw/pci-host/
H A Darticia.c44 bitbang_i2c_interface smbus; member
71 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA, in articia_gpio_write()
76 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SCL, in articia_gpio_write()
174 bitbang_i2c_init(&s->smbus, i2c_init_bus(dev, "smbus")); in articia_realize()
/qemu/hw/arm/
H A Dnpcm8xx.c239 /* Direct memory-mapped access to each SMBus Module. */
436 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm8xx_init()
437 object_initialize_child(obj, "smbus[*]", &s->smbus[i], in npcm8xx_init()
439 DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i); in npcm8xx_init()
633 /* SMBus modules. Cannot fail. */ in npcm8xx_realize()
634 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus)); in npcm8xx_realize()
635 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm8xx_realize()
636 Object *obj = OBJECT(&s->smbus[i]); in npcm8xx_realize()
H A Dnpcm7xx.c203 /* Direct memory-mapped access to each SMBus Module. */
443 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm7xx_init()
444 object_initialize_child(obj, "smbus[*]", &s->smbus[i], in npcm7xx_init()
619 /* SMBus modules. Cannot fail. */ in npcm7xx_realize()
620 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); in npcm7xx_realize()
621 for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { in npcm7xx_realize()
622 Object *obj = OBJECT(&s->smbus[i]); in npcm7xx_realize()
H A DKconfig462 select SMBUS
479 select SMBUS
H A Dnpcm8xx_boards.c96 g_assert(num < ARRAY_SIZE(soc->smbus)); in npcm8xx_i2c_get_bus()
97 return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); in npcm8xx_i2c_get_bus()
/qemu/hw/ipmi/
H A Dsmbus_ipmi.c2 * QEMU IPMI SMBus (SSIF) emulation
33 #define TYPE_SMBUS_IPMI "smbus-ipmi"
58 /* Holds the SMBUS message currently being sent to the host. */
343 info->interface_name = "smbus"; in smbus_ipmi_get_fwinfo()
/qemu/tests/qtest/
H A Dnpcm7xx_smbus-test.c2 * QTests for Nuvoton NPCM7xx SMBus Modules.
338 /* Check the SMBus's status is set correctly when disabled. */
353 /* Check the SMBus returns a NACK for an invalid address. */
375 /* Check the SMBus can send and receive bytes to a device in single mode. */
411 /* Check the SMBus can send and receive bytes in FIFO mode. */
/qemu/hw/mips/
H A Dfuloong2e.c223 I2CBus *smbus; in mips_fuloong2e_init() local
309 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); in mips_fuloong2e_init()
323 smbus_eeprom_init_one(smbus, 0x50, spd_data); in mips_fuloong2e_init()
/qemu/include/hw/southbridge/
H A Dich9.h213 /* D31:F3 SMBus controller */
232 /* D31:F3 SMBus I/O and memory mapped I/O registers */
/qemu/hw/net/
H A De1000x_regs.h920 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
947 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
948 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
949 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
950 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
951 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
952 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
954 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
955 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
/qemu/include/hw/i386/
H A Dpc.h35 I2CBus *smbus; member
66 #define PC_MACHINE_SMBUS "smbus"
/qemu/docs/system/
H A Dtarget-mips.rst24 - PIIX4 PCI/USB/SMbus controller
/qemu/include/hw/arm/
H A Dnpcm8xx.h99 NPCM7xxSMBusState smbus[27]; member

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