xref: /qemu/hw/i2c/smbus_slave.c (revision 12d1a768bdfea6e27a3a829228840d72507613a1)
10ff596d0Spbrook /*
20ff596d0Spbrook  * QEMU SMBus device emulation.
30ff596d0Spbrook  *
493198b6cSCorey Minyard  * This code is a helper for SMBus device emulation.  It implements an
58fa21b80SMichael Tokarev  * I2C device interface and runs the SMBus protocol from the device
693198b6cSCorey Minyard  * point of view and maps those to simple calls to emulate.
793198b6cSCorey Minyard  *
80ff596d0Spbrook  * Copyright (c) 2007 CodeSourcery.
90ff596d0Spbrook  * Written by Paul Brook
100ff596d0Spbrook  *
118e31bf38SMatthew Fernandez  * This code is licensed under the LGPL.
120ff596d0Spbrook  */
130ff596d0Spbrook 
140ff596d0Spbrook /* TODO: Implement PEC.  */
150ff596d0Spbrook 
160430891cSPeter Maydell #include "qemu/osdep.h"
170d09e41aSPaolo Bonzini #include "hw/i2c/i2c.h"
1893198b6cSCorey Minyard #include "hw/i2c/smbus_slave.h"
19d6454270SMarkus Armbruster #include "migration/vmstate.h"
200b8fa32fSMarkus Armbruster #include "qemu/module.h"
210ff596d0Spbrook 
220ff596d0Spbrook //#define DEBUG_SMBUS 1
230ff596d0Spbrook 
240ff596d0Spbrook #ifdef DEBUG_SMBUS
25001faf32SBlue Swirl #define DPRINTF(fmt, ...) \
26001faf32SBlue Swirl do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
27001faf32SBlue Swirl #define BADF(fmt, ...) \
28fcc8299eSJoe Komlodi do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
29fcc8299eSJoe Komlodi     fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
30fcc8299eSJoe Komlodi             exit(1); } while (0)
310ff596d0Spbrook #else
32001faf32SBlue Swirl #define DPRINTF(fmt, ...) do {} while(0)
33001faf32SBlue Swirl #define BADF(fmt, ...) \
34fcc8299eSJoe Komlodi do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
35fcc8299eSJoe Komlodi     fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
36fcc8299eSJoe Komlodi              } while (0)
370ff596d0Spbrook #endif
380ff596d0Spbrook 
390ff596d0Spbrook enum {
400ff596d0Spbrook     SMBUS_IDLE,
410ff596d0Spbrook     SMBUS_WRITE_DATA,
420ff596d0Spbrook     SMBUS_READ_DATA,
430ff596d0Spbrook     SMBUS_DONE,
440ff596d0Spbrook     SMBUS_CONFUSED = -1
450ff596d0Spbrook };
460ff596d0Spbrook 
smbus_do_quick_cmd(SMBusDevice * dev,int recv)470ff596d0Spbrook static void smbus_do_quick_cmd(SMBusDevice *dev, int recv)
480ff596d0Spbrook {
49b5ea9327SAnthony Liguori     SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
501ea96673SPaul Brook 
510ff596d0Spbrook     DPRINTF("Quick Command %d\n", recv);
52b5ea9327SAnthony Liguori     if (sc->quick_cmd) {
53b5ea9327SAnthony Liguori         sc->quick_cmd(dev, recv);
54b5ea9327SAnthony Liguori     }
550ff596d0Spbrook }
560ff596d0Spbrook 
smbus_do_write(SMBusDevice * dev)570ff596d0Spbrook static void smbus_do_write(SMBusDevice *dev)
580ff596d0Spbrook {
59b5ea9327SAnthony Liguori     SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
601ea96673SPaul Brook 
619cf27d74SCorey Minyard     DPRINTF("Command %d len %d\n", dev->data_buf[0], dev->data_len);
62b5ea9327SAnthony Liguori     if (sc->write_data) {
639cf27d74SCorey Minyard         sc->write_data(dev, dev->data_buf, dev->data_len);
640ff596d0Spbrook     }
650ff596d0Spbrook }
660ff596d0Spbrook 
smbus_i2c_event(I2CSlave * s,enum i2c_event event)67d307c28cSCorey Minyard static int smbus_i2c_event(I2CSlave *s, enum i2c_event event)
680ff596d0Spbrook {
69b5ea9327SAnthony Liguori     SMBusDevice *dev = SMBUS_DEVICE(s);
701ea96673SPaul Brook 
710ff596d0Spbrook     switch (event) {
720ff596d0Spbrook     case I2C_START_SEND:
730ff596d0Spbrook         switch (dev->mode) {
740ff596d0Spbrook         case SMBUS_IDLE:
750ff596d0Spbrook             DPRINTF("Incoming data\n");
760ff596d0Spbrook             dev->mode = SMBUS_WRITE_DATA;
770ff596d0Spbrook             break;
788b38e532SCorey Minyard 
790ff596d0Spbrook         default:
800ff596d0Spbrook             BADF("Unexpected send start condition in state %d\n", dev->mode);
810ff596d0Spbrook             dev->mode = SMBUS_CONFUSED;
820ff596d0Spbrook             break;
830ff596d0Spbrook         }
840ff596d0Spbrook         break;
850ff596d0Spbrook 
860ff596d0Spbrook     case I2C_START_RECV:
870ff596d0Spbrook         switch (dev->mode) {
880ff596d0Spbrook         case SMBUS_IDLE:
890ff596d0Spbrook             DPRINTF("Read mode\n");
90031ac498SCorey Minyard             dev->mode = SMBUS_READ_DATA;
910ff596d0Spbrook             break;
928b38e532SCorey Minyard 
930ff596d0Spbrook         case SMBUS_WRITE_DATA:
940ff596d0Spbrook             if (dev->data_len == 0) {
950ff596d0Spbrook                 BADF("Read after write with no data\n");
960ff596d0Spbrook                 dev->mode = SMBUS_CONFUSED;
970ff596d0Spbrook             } else {
980ff596d0Spbrook                 smbus_do_write(dev);
990ff596d0Spbrook                 DPRINTF("Read mode\n");
1000ff596d0Spbrook                 dev->mode = SMBUS_READ_DATA;
1010ff596d0Spbrook             }
1020ff596d0Spbrook             break;
1038b38e532SCorey Minyard 
1040ff596d0Spbrook         default:
1050ff596d0Spbrook             BADF("Unexpected recv start condition in state %d\n", dev->mode);
1060ff596d0Spbrook             dev->mode = SMBUS_CONFUSED;
1070ff596d0Spbrook             break;
1080ff596d0Spbrook         }
1090ff596d0Spbrook         break;
1100ff596d0Spbrook 
1110ff596d0Spbrook     case I2C_FINISH:
112905cec6dSCorey Minyard         if (dev->data_len == 0) {
113905cec6dSCorey Minyard             if (dev->mode == SMBUS_WRITE_DATA || dev->mode == SMBUS_READ_DATA) {
114905cec6dSCorey Minyard                 smbus_do_quick_cmd(dev, dev->mode == SMBUS_READ_DATA);
115905cec6dSCorey Minyard             }
116905cec6dSCorey Minyard         } else {
1170ff596d0Spbrook             switch (dev->mode) {
1180ff596d0Spbrook             case SMBUS_WRITE_DATA:
1190ff596d0Spbrook                 smbus_do_write(dev);
1200ff596d0Spbrook                 break;
121905cec6dSCorey Minyard 
1220ff596d0Spbrook             case SMBUS_READ_DATA:
1230ff596d0Spbrook                 BADF("Unexpected stop during receive\n");
1240ff596d0Spbrook                 break;
125905cec6dSCorey Minyard 
1260ff596d0Spbrook             default:
1270ff596d0Spbrook                 /* Nothing to do.  */
1280ff596d0Spbrook                 break;
1290ff596d0Spbrook             }
130905cec6dSCorey Minyard         }
1310ff596d0Spbrook         dev->mode = SMBUS_IDLE;
1320ff596d0Spbrook         dev->data_len = 0;
1330ff596d0Spbrook         break;
1340ff596d0Spbrook 
1350ff596d0Spbrook     case I2C_NACK:
1360ff596d0Spbrook         switch (dev->mode) {
1370ff596d0Spbrook         case SMBUS_DONE:
1380ff596d0Spbrook             /* Nothing to do.  */
1390ff596d0Spbrook             break;
1408b38e532SCorey Minyard 
1410ff596d0Spbrook         case SMBUS_READ_DATA:
1420ff596d0Spbrook             dev->mode = SMBUS_DONE;
1430ff596d0Spbrook             break;
1448b38e532SCorey Minyard 
1450ff596d0Spbrook         default:
1460ff596d0Spbrook             BADF("Unexpected NACK in state %d\n", dev->mode);
1470ff596d0Spbrook             dev->mode = SMBUS_CONFUSED;
1480ff596d0Spbrook             break;
1490ff596d0Spbrook         }
150a78e9839SKlaus Jensen         break;
151a78e9839SKlaus Jensen 
152a78e9839SKlaus Jensen     default:
153a78e9839SKlaus Jensen         return -1;
1540ff596d0Spbrook     }
155d307c28cSCorey Minyard 
156d307c28cSCorey Minyard     return 0;
1570ff596d0Spbrook }
1580ff596d0Spbrook 
smbus_i2c_recv(I2CSlave * s)1592ac4c5f4SCorey Minyard static uint8_t smbus_i2c_recv(I2CSlave *s)
1600ff596d0Spbrook {
161b5ea9327SAnthony Liguori     SMBusDevice *dev = SMBUS_DEVICE(s);
162b5ea9327SAnthony Liguori     SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
163031ac498SCorey Minyard     uint8_t ret = 0xff;
1640ff596d0Spbrook 
1650ff596d0Spbrook     switch (dev->mode) {
166031ac498SCorey Minyard     case SMBUS_READ_DATA:
167b5ea9327SAnthony Liguori         if (sc->receive_byte) {
168b5ea9327SAnthony Liguori             ret = sc->receive_byte(dev);
1690ff596d0Spbrook         }
1700ff596d0Spbrook         DPRINTF("Read data %02x\n", ret);
1710ff596d0Spbrook         break;
1728b38e532SCorey Minyard 
1730ff596d0Spbrook     default:
1740ff596d0Spbrook         BADF("Unexpected read in state %d\n", dev->mode);
1750ff596d0Spbrook         dev->mode = SMBUS_CONFUSED;
1760ff596d0Spbrook         break;
1770ff596d0Spbrook     }
1788b38e532SCorey Minyard 
1790ff596d0Spbrook     return ret;
1800ff596d0Spbrook }
1810ff596d0Spbrook 
smbus_i2c_send(I2CSlave * s,uint8_t data)1829e07bdf8SAnthony Liguori static int smbus_i2c_send(I2CSlave *s, uint8_t data)
1830ff596d0Spbrook {
184b5ea9327SAnthony Liguori     SMBusDevice *dev = SMBUS_DEVICE(s);
1851ea96673SPaul Brook 
1860ff596d0Spbrook     switch (dev->mode) {
1870ff596d0Spbrook     case SMBUS_WRITE_DATA:
1880ff596d0Spbrook         DPRINTF("Write data %02x\n", data);
189629457a1SCorey Minyard         if (dev->data_len >= sizeof(dev->data_buf)) {
190629457a1SCorey Minyard             BADF("Too many bytes sent\n");
191629457a1SCorey Minyard         } else {
1920ff596d0Spbrook             dev->data_buf[dev->data_len++] = data;
193629457a1SCorey Minyard         }
1940ff596d0Spbrook         break;
1958b38e532SCorey Minyard 
1960ff596d0Spbrook     default:
1970ff596d0Spbrook         BADF("Unexpected write in state %d\n", dev->mode);
1980ff596d0Spbrook         break;
1990ff596d0Spbrook     }
2008b38e532SCorey Minyard 
2010ff596d0Spbrook     return 0;
2020ff596d0Spbrook }
2030ff596d0Spbrook 
smbus_device_class_init(ObjectClass * klass,const void * data)204*12d1a768SPhilippe Mathieu-Daudé static void smbus_device_class_init(ObjectClass *klass, const void *data)
205b5ea9327SAnthony Liguori {
206b5ea9327SAnthony Liguori     I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
207b5ea9327SAnthony Liguori 
208b5ea9327SAnthony Liguori     sc->event = smbus_i2c_event;
209b5ea9327SAnthony Liguori     sc->recv = smbus_i2c_recv;
210b5ea9327SAnthony Liguori     sc->send = smbus_i2c_send;
211b5ea9327SAnthony Liguori }
212b5ea9327SAnthony Liguori 
smbus_vmstate_needed(SMBusDevice * dev)213547db24aSCorey Minyard bool smbus_vmstate_needed(SMBusDevice *dev)
214547db24aSCorey Minyard {
215547db24aSCorey Minyard     return dev->mode != SMBUS_IDLE;
216547db24aSCorey Minyard }
217547db24aSCorey Minyard 
218547db24aSCorey Minyard const VMStateDescription vmstate_smbus_device = {
219547db24aSCorey Minyard     .name = TYPE_SMBUS_DEVICE,
220547db24aSCorey Minyard     .version_id = 1,
221547db24aSCorey Minyard     .minimum_version_id = 1,
22201d9442aSRichard Henderson     .fields = (const VMStateField[]) {
223547db24aSCorey Minyard         VMSTATE_I2C_SLAVE(i2c, SMBusDevice),
224547db24aSCorey Minyard         VMSTATE_INT32(mode, SMBusDevice),
225547db24aSCorey Minyard         VMSTATE_INT32(data_len, SMBusDevice),
226547db24aSCorey Minyard         VMSTATE_UINT8_ARRAY(data_buf, SMBusDevice, SMBUS_DATA_MAX_LEN),
227547db24aSCorey Minyard         VMSTATE_END_OF_LIST()
228547db24aSCorey Minyard     }
229547db24aSCorey Minyard };
230547db24aSCorey Minyard 
2318c43a6f0SAndreas Färber static const TypeInfo smbus_device_type_info = {
232b5ea9327SAnthony Liguori     .name = TYPE_SMBUS_DEVICE,
233b5ea9327SAnthony Liguori     .parent = TYPE_I2C_SLAVE,
234b5ea9327SAnthony Liguori     .instance_size = sizeof(SMBusDevice),
235b5ea9327SAnthony Liguori     .abstract = true,
236b5ea9327SAnthony Liguori     .class_size = sizeof(SMBusDeviceClass),
237b5ea9327SAnthony Liguori     .class_init = smbus_device_class_init,
238b5ea9327SAnthony Liguori };
239b5ea9327SAnthony Liguori 
smbus_device_register_types(void)24083f7d43aSAndreas Färber static void smbus_device_register_types(void)
241b5ea9327SAnthony Liguori {
242b5ea9327SAnthony Liguori     type_register_static(&smbus_device_type_info);
243b5ea9327SAnthony Liguori }
244b5ea9327SAnthony Liguori 
24583f7d43aSAndreas Färber type_init(smbus_device_register_types)
246