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/linux-6.15/Documentation/devicetree/bindings/interconnect/
Dqcom,sm8650-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
21 See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
26 - qcom,sm8650-aggre1-noc
27 - qcom,sm8650-aggre2-noc
28 - qcom,sm8650-clk-virt
29 - qcom,sm8650-cnoc-main
30 - qcom,sm8650-config-noc
31 - qcom,sm8650-gem-noc
32 - qcom,sm8650-lpass-ag-noc
[all …]
Dqcom,msm8998-bwmon.yaml40 - qcom,sm8650-cpu-bwmon
54 - qcom,sm8650-llcc-bwmon
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm8650-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8650 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
20 - const: qcom,sm8650-lpass-lpi-pinctrl
23 - const: qcom,sm8650-lpass-lpi-pinctrl
42 - $ref: "#/$defs/qcom-sm8650-lpass-state"
45 $ref: "#/$defs/qcom-sm8650-lpass-state"
49 qcom-sm8650-lpass-state:
94 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
Dqcom,sm8650-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM8650 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
20 const: qcom,sm8650-tlmm
38 - $ref: "#/$defs/qcom-sm8650-tlmm-state"
41 $ref: "#/$defs/qcom-sm8650-tlmm-state"
45 qcom-sm8650-tlmm-state:
113 compatible = "qcom,sm8650-tlmm";
/linux-6.15/Documentation/devicetree/bindings/display/msm/
Dqcom,sm8650-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
7 title: Qualcomm SM8650 Display MDSS
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
20 const: qcom,sm8650-mdss
47 const: qcom,sm8650-dpu
54 const: qcom,sm8650-dp
62 - const: qcom,sm8650-dsi-ctrl
70 const: qcom,sm8650-dsi-phy-4nm
82 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
85 compatible = "qcom,sm8650-mdss";
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Dqcom,sm8650-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
7 title: Qualcomm SM8650 Display DPU
18 - qcom,sm8650-dpu
62 compatible = "qcom,sm8650-dpu";
/linux-6.15/Documentation/devicetree/bindings/remoteproc/
Dqcom,sm8550-pas.yaml24 - qcom,sm8650-adsp-pas
25 - qcom,sm8650-cdsp-pas
26 - qcom,sm8650-mpss-pas
35 - const: qcom,sm8650-cdsp-pas
82 - qcom,sm8650-adsp-pas
111 - qcom,sm8650-cdsp-pas
157 - qcom,sm8650-mpss-pas
189 - qcom,sm8650-adsp-pas
209 - qcom,sm8650-mpss-pas
227 - qcom,sm8650-cdsp-pas
/linux-6.15/Documentation/devicetree/bindings/clock/
Dqcom,sm8650-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8650
14 domains on SM8650
16 See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
20 const: qcom,sm8650-gcc
49 compatible = "qcom,sm8650-gcc";
Dqcom,sm8550-dispcc.yaml15 domains on SM8550, SM8650, SM8750 and few other platforms.
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
28 - qcom,sm8650-dispcc
Dqcom,sm8550-tcsr.yaml18 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
27 - qcom,sm8650-tcsr
Dqcom,sm8450-gpucc.yaml22 include/dt-bindings/reset/qcom,sm8650-gpucc.h
33 - qcom,sm8650-gpucc
Dqcom,sm8450-videocc.yaml19 include/dt-bindings/clock/qcom,sm8650-videocc.h
27 - qcom,sm8650-videocc
Dqcom,sm8450-camcc.yaml21 include/dt-bindings/clock/qcom,sm8650-camcc.h
30 - qcom,sm8650-camcc
/linux-6.15/arch/arm64/boot/dts/qcom/
Dsm8650.dtsi7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
17 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
23 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
404 compatible = "qcom,scm-sm8650", "qcom,scm";
412 compatible = "qcom,sm8650-clk-virt";
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Dsm8650-mtp.dts9 #include "sm8650.dtsi"
20 model = "Qualcomm Technologies, Inc. SM8650 MTP";
21 compatible = "qcom,sm8650-mtp", "qcom,sm8650";
32 compatible = "qcom,sm8650-pmic-glink",
70 compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
71 model = "SM8650-MTP";
696 firmware-name = "qcom/sm8650/adsp.mbn",
697 "qcom/sm8650/adsp_dtb.mbn";
703 firmware-name = "qcom/sm8650/cdsp.mbn",
704 "qcom/sm8650/cdsp_dtb.mbn";
[all …]
Dsm8650-qrd.dts10 #include "sm8650.dtsi"
21 model = "Qualcomm Technologies, Inc. SM8650 QRD";
22 compatible = "qcom,sm8650-qrd", "qcom,sm8650";
50 compatible = "qcom,sm8650-pmic-glink",
96 compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
97 model = "SM8650-QRD";
823 firmware-name = "qcom/sm8650/ipa_fws.mbn";
831 firmware-name = "qcom/sm8650/gen70900_zap.mbn";
1023 firmware-name = "qcom/sm8650/adsp.mbn",
1024 "qcom/sm8650/adsp_dtb.mbn";
[all …]
Dsm8650-hdk.dts10 #include "sm8650.dtsi"
20 model = "Qualcomm Technologies, Inc. SM8650 HDK";
21 compatible = "qcom,sm8650-hdk", "qcom,sm8650";
89 compatible = "qcom,sm8650-pmic-glink",
161 compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
162 model = "SM8650-HDK";
893 firmware-name = "qcom/sm8650/ipa_fws.mbn";
901 firmware-name = "qcom/sm8650/gen70900_zap.mbn";
1079 firmware-name = "qcom/sm8650/adsp.mbn",
1080 "qcom/sm8650/adsp_dtb.mbn";
[all …]
DMakefile283 sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
285 dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
286 dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
287 dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
288 dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
/linux-6.15/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-pcie-phy.yaml43 - qcom,sm8650-qmp-gen3x2-pcie-phy
44 - qcom,sm8650-qmp-gen4x2-pcie-phy
164 - qcom,sm8650-qmp-gen3x2-pcie-phy
165 - qcom,sm8650-qmp-gen4x2-pcie-phy
215 - qcom,sm8650-qmp-gen4x2-pcie-phy
233 - qcom,sm8650-qmp-gen4x2-pcie-phy
/linux-6.15/drivers/clk/qcom/
Dtcsrcc-sm8650.c14 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
151 { .compatible = "qcom,sm8650-tcsr" },
164 .name = "tcsr_cc-sm8650",
181 MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");
DMakefile128 obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
150 obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
162 obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
165 obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
DKconfig962 tristate "SM8650 Camera Clock Controller"
966 Support for the camera clock controller on SM8650 devices.
1055 SAR2130P, SM8550 or SM8650 devices.
1171 tristate "SM8650 Global Clock Controller"
1175 Support for the global clock controller on SM8650 devices.
1280 tristate "SM8650 Graphics Clock Controller"
1284 Support for the graphics clock controller on SM8650 devices.
1306 tristate "SM8650 TCSR Clock Controller"
1310 Support for the TCSR clock controller on SM8650 devices.
1379 SM8550 or SM8650 devices.
/linux-6.15/drivers/interconnect/qcom/
Dsm8650.c13 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include "sm8650.h"
1633 { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc },
1634 { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc },
1635 { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt },
1636 { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc },
1637 { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main },
1638 { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc },
1639 { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc },
1640 { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc },
[all …]
DMakefile42 qnoc-sm8650-objs := sm8650.o
83 obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o
/linux-6.15/drivers/pinctrl/qcom/
Dpinctrl-sm8650-lpass-lpi.c213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",
222 .name = "qcom-sm8650-lpass-lpi-pinctrl",
230 MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");

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