1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8650 Display MDSS
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12description:
13  SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8650-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    items:
33      - description: Interconnect path from mdp0 port to the data bus
34      - description: Interconnect path from CPU to the reg bus
35
36  interconnect-names:
37    items:
38      - const: mdp0-mem
39      - const: cpu-cfg
40
41patternProperties:
42  "^display-controller@[0-9a-f]+$":
43    type: object
44    additionalProperties: true
45    properties:
46      compatible:
47        const: qcom,sm8650-dpu
48
49  "^displayport-controller@[0-9a-f]+$":
50    type: object
51    additionalProperties: true
52    properties:
53      compatible:
54        const: qcom,sm8650-dp
55
56  "^dsi@[0-9a-f]+$":
57    type: object
58    additionalProperties: true
59    properties:
60      compatible:
61        items:
62          - const: qcom,sm8650-dsi-ctrl
63          - const: qcom,mdss-dsi-ctrl
64
65  "^phy@[0-9a-f]+$":
66    type: object
67    additionalProperties: true
68    properties:
69      compatible:
70        const: qcom,sm8650-dsi-phy-4nm
71
72required:
73  - compatible
74
75unevaluatedProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/qcom,rpmh.h>
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/power/qcom,rpmhpd.h>
82    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
83
84    display-subsystem@ae00000 {
85        compatible = "qcom,sm8650-mdss";
86        reg = <0x0ae00000 0x1000>;
87        reg-names = "mdss";
88
89        interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
90                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
91        interconnect-names = "mdp0-mem", "cpu-cfg";
92
93        resets = <&dispcc_core_bcr>;
94
95        power-domains = <&dispcc_gdsc>;
96
97        clocks = <&gcc_ahb_clk>,
98                 <&gcc_axi_clk>,
99                 <&dispcc_mdp_clk>;
100        clock-names = "bus", "nrt_bus", "core";
101
102        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
103        interrupt-controller;
104        #interrupt-cells = <1>;
105
106        iommus = <&apps_smmu 0x1c00 0x2>;
107
108        #address-cells = <1>;
109        #size-cells = <1>;
110        ranges;
111
112        display-controller@ae01000 {
113            compatible = "qcom,sm8650-dpu";
114            reg = <0x0ae01000 0x8f000>,
115                  <0x0aeb0000 0x2008>;
116            reg-names = "mdp", "vbif";
117
118            clocks = <&gcc_axi_clk>,
119                     <&dispcc_ahb_clk>,
120                     <&dispcc_mdp_lut_clk>,
121                     <&dispcc_mdp_clk>,
122                     <&dispcc_mdp_vsync_clk>;
123            clock-names = "nrt_bus",
124                          "iface",
125                          "lut",
126                          "core",
127                          "vsync";
128
129            assigned-clocks = <&dispcc_mdp_vsync_clk>;
130            assigned-clock-rates = <19200000>;
131
132            operating-points-v2 = <&mdp_opp_table>;
133            power-domains = <&rpmhpd RPMHPD_MMCX>;
134
135            interrupt-parent = <&mdss>;
136            interrupts = <0>;
137
138            ports {
139                #address-cells = <1>;
140                #size-cells = <0>;
141
142                port@0 {
143                    reg = <0>;
144                    dpu_intf1_out: endpoint {
145                        remote-endpoint = <&dsi0_in>;
146                    };
147                };
148
149                port@1 {
150                    reg = <1>;
151                    dpu_intf2_out: endpoint {
152                        remote-endpoint = <&dsi1_in>;
153                    };
154                };
155            };
156
157            mdp_opp_table: opp-table {
158                compatible = "operating-points-v2";
159
160                opp-200000000 {
161                    opp-hz = /bits/ 64 <200000000>;
162                    required-opps = <&rpmhpd_opp_low_svs>;
163                };
164
165                opp-325000000 {
166                    opp-hz = /bits/ 64 <325000000>;
167                    required-opps = <&rpmhpd_opp_svs>;
168                };
169
170                opp-375000000 {
171                    opp-hz = /bits/ 64 <375000000>;
172                    required-opps = <&rpmhpd_opp_svs_l1>;
173                };
174
175                opp-514000000 {
176                    opp-hz = /bits/ 64 <514000000>;
177                    required-opps = <&rpmhpd_opp_nom>;
178                };
179            };
180        };
181
182        dsi@ae94000 {
183            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
184            reg = <0x0ae94000 0x400>;
185            reg-names = "dsi_ctrl";
186
187            interrupt-parent = <&mdss>;
188            interrupts = <4>;
189
190            clocks = <&dispc_byte_clk>,
191                     <&dispcc_intf_clk>,
192                     <&dispcc_pclk>,
193                     <&dispcc_esc_clk>,
194                     <&dispcc_ahb_clk>,
195                     <&gcc_bus_clk>;
196            clock-names = "byte",
197                          "byte_intf",
198                          "pixel",
199                          "core",
200                          "iface",
201                          "bus";
202
203            assigned-clocks = <&dispcc_byte_clk>,
204                              <&dispcc_pclk>;
205            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
206
207            operating-points-v2 = <&dsi_opp_table>;
208            power-domains = <&rpmhpd RPMHPD_MMCX>;
209
210            phys = <&dsi0_phy>;
211            phy-names = "dsi";
212
213            #address-cells = <1>;
214            #size-cells = <0>;
215
216            ports {
217                #address-cells = <1>;
218                #size-cells = <0>;
219
220                port@0 {
221                    reg = <0>;
222                    dsi0_in: endpoint {
223                        remote-endpoint = <&dpu_intf1_out>;
224                    };
225                };
226
227                port@1 {
228                    reg = <1>;
229                    dsi0_out: endpoint {
230                    };
231                };
232            };
233
234            dsi_opp_table: opp-table {
235                compatible = "operating-points-v2";
236
237                opp-187500000 {
238                    opp-hz = /bits/ 64 <187500000>;
239                    required-opps = <&rpmhpd_opp_low_svs>;
240                };
241
242                opp-300000000 {
243                    opp-hz = /bits/ 64 <300000000>;
244                    required-opps = <&rpmhpd_opp_svs>;
245                };
246
247                opp-358000000 {
248                    opp-hz = /bits/ 64 <358000000>;
249                    required-opps = <&rpmhpd_opp_svs_l1>;
250                };
251            };
252        };
253
254        dsi0_phy: phy@ae94400 {
255            compatible = "qcom,sm8650-dsi-phy-4nm";
256            reg = <0x0ae95000 0x200>,
257                  <0x0ae95200 0x280>,
258                  <0x0ae95500 0x400>;
259            reg-names = "dsi_phy",
260                        "dsi_phy_lane",
261                        "dsi_pll";
262
263            #clock-cells = <1>;
264            #phy-cells = <0>;
265
266            clocks = <&dispcc_iface_clk>,
267                     <&rpmhcc_ref_clk>;
268            clock-names = "iface", "ref";
269        };
270
271        dsi@ae96000 {
272            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
273            reg = <0x0ae96000 0x400>;
274            reg-names = "dsi_ctrl";
275
276            interrupt-parent = <&mdss>;
277            interrupts = <5>;
278
279            clocks = <&dispc_byte_clk>,
280                     <&dispcc_intf_clk>,
281                     <&dispcc_pclk>,
282                     <&dispcc_esc_clk>,
283                     <&dispcc_ahb_clk>,
284                     <&gcc_bus_clk>;
285            clock-names = "byte",
286                          "byte_intf",
287                          "pixel",
288                          "core",
289                          "iface",
290                          "bus";
291
292            assigned-clocks = <&dispcc_byte_clk>,
293                              <&dispcc_pclk>;
294            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
295
296            operating-points-v2 = <&dsi_opp_table>;
297            power-domains = <&rpmhpd RPMHPD_MMCX>;
298
299            phys = <&dsi1_phy>;
300            phy-names = "dsi";
301
302            #address-cells = <1>;
303            #size-cells = <0>;
304
305            ports {
306                #address-cells = <1>;
307                #size-cells = <0>;
308
309                port@0 {
310                    reg = <0>;
311                    dsi1_in: endpoint {
312                        remote-endpoint = <&dpu_intf2_out>;
313                    };
314                };
315
316                port@1 {
317                    reg = <1>;
318                    dsi1_out: endpoint {
319                    };
320                };
321            };
322        };
323
324        dsi1_phy: phy@ae96400 {
325            compatible = "qcom,sm8650-dsi-phy-4nm";
326            reg = <0x0ae97000 0x200>,
327                  <0x0ae97200 0x280>,
328                  <0x0ae97500 0x400>;
329            reg-names = "dsi_phy",
330                        "dsi_phy_lane",
331                        "dsi_pll";
332
333            #clock-cells = <1>;
334            #phy-cells = <0>;
335
336            clocks = <&dispcc_iface_clk>,
337                     <&rpmhcc_ref_clk>;
338            clock-names = "iface", "ref";
339        };
340    };
341...
342