1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Camera Clock & Reset Controller on SM8450
8
9maintainers:
10  - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm camera clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,sc8280xp-camcc.h
19    include/dt-bindings/clock/qcom,sm8450-camcc.h
20    include/dt-bindings/clock/qcom,sm8550-camcc.h
21    include/dt-bindings/clock/qcom,sm8650-camcc.h
22
23properties:
24  compatible:
25    enum:
26      - qcom,sc8280xp-camcc
27      - qcom,sm8450-camcc
28      - qcom,sm8475-camcc
29      - qcom,sm8550-camcc
30      - qcom,sm8650-camcc
31
32  clocks:
33    items:
34      - description: Camera AHB clock from GCC
35      - description: Board XO source
36      - description: Board active XO source
37      - description: Sleep clock source
38
39  power-domains:
40    maxItems: 1
41    description:
42      A phandle and PM domain specifier for the MMCX power domain.
43
44  required-opps:
45    maxItems: 1
46    description:
47      A phandle to an OPP node describing required MMCX performance point.
48
49  reg:
50    maxItems: 1
51
52required:
53  - compatible
54  - clocks
55  - power-domains
56
57allOf:
58  - $ref: qcom,gcc.yaml#
59  - if:
60      properties:
61        compatible:
62          contains:
63            enum:
64              - qcom,sc8280xp-camcc
65              - qcom,sm8450-camcc
66              - qcom,sm8550-camcc
67    then:
68      required:
69        - required-opps
70
71unevaluatedProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/power/qcom,rpmhpd.h>
78    clock-controller@ade0000 {
79      compatible = "qcom,sm8450-camcc";
80      reg = <0xade0000 0x20000>;
81      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
82               <&rpmhcc RPMH_CXO_CLK>,
83               <&rpmhcc RPMH_CXO_CLK_A>,
84               <&sleep_clk>;
85      power-domains = <&rpmhpd RPMHPD_MMCX>;
86      required-opps = <&rpmhpd_opp_low_svs>;
87      #clock-cells = <1>;
88      #reset-cells = <1>;
89      #power-domain-cells = <1>;
90    };
91...
92