| /qemu/hw/net/fsl_etsec/ |
| H A D | registers.c | 40 {0x058, "FIFO_RX_ALARM", "FIFO receive alarm start threshold register", ACC_RW, 0x00000…
41 {0x05C, "FIFO_RX_ALARM_SHUTOFF", "FIFO receive alarm shut-off threshold register", ACC_RW, 0x00000…
80 /* eTSEC Receive Control and Status Registers */
82 {0x300, "RCTRL", "Receive control register", ACC_RW, 0x00000000},
83 {0x304, "RSTAT", "Receive status register", ACC_W1C, 0x00000000},
84 {0x310, "RXIC", "Receive interrupt coalescing register", ACC_RW, 0x00000000},
85 {0x314, "RQUEUE", "Receive queue control register.", ACC_RW, 0x00800080},
86 {0x330, "RBIFX", "Receive bit field extract control register", ACC_RW, 0x00000000},
87 {0x334, "RQFAR", "Receive queue filing table address register", ACC_RW, 0x00000000},
88 {0x338, "RQFCR", "Receive queue filing table control register", ACC_RW, 0x00000000},
[all …]
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| /qemu/include/hw/net/ |
| H A D | npcm_gmac.h | 71 /* Receive Watchdog Timeout */
73 /* Receive Error */
84 /* Receive end of ring */
88 /* Receive Buffer 2 Size */
92 /* Receive Buffer 1 Size */
195 /* Receive States */
210 /* Early Receive Interrupt */
216 /* Receive Watchdog Timeout */
218 /* Receive Process Stopped */
220 /* Receive Buffer Unavailable */
[all …]
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| H A D | npcm7xx_emc.h | 113 /* Enable Receive Descriptor Unavailable Interrupt */
115 /* Enable Receive Good Interrupt */
117 /* Enable Receive Interrupt */
130 /* Receive Bus Error Interrupt */
132 /* Receive Descriptor Unavailable Interrupt */
138 /* Receive Good Interrupt */
142 /* Receive Interrupt */
148 /* Receive Halted */
152 /* Maximum Receive Frame Length */
159 /* Transmit and receive descriptors */
[all …]
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| H A D | allwinner-sun8i-emac.h | 84 uint32_t frm_flt; /**< Receive Frame Filter */
86 uint32_t rx_ctl0; /**< Receive Control 0 */
87 uint32_t rx_ctl1; /**< Receive Control 1 */
88 uint32_t rx_desc_head; /**< Receive Descriptor List Address */
89 uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
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| /qemu/hw/net/ |
| H A D | allwinner-sun8i-emac.c | 46 REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
47 REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
48 REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
49 REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
50 REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
51 REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
59 REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
60 REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
61 REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
157 /* Transmit/receive frame descriptor */
[all …]
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| H A D | xgmac.c | 73 #define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */
79 /* Receive Interrupt Watchdog Timer */
97 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
101 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
104 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
105 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
106 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
107 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
109 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
117 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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| H A D | e1000x_regs.h | 152 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
154 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
155 #define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
157 #define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
159 #define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
160 #define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
161 #define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
172 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
181 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
228 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
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| H A D | i82596.c | 535 /* promiscuous: receive all */ in i82596_receive()
591 rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ in i82596_receive()
594 /* get first Receive Buffer Descriptor Address */ in i82596_receive()
599 /* PRINT_PKTHDR("Receive", buf); */ in i82596_receive()
607 /* get first Receive Buffer Descriptor Address */ in i82596_receive()
611 /* printf("Receive: rfd is %08x\n", rfd_p); */ in i82596_receive()
618 /* printf("Receive: rbd is %08x\n", rbd); */ in i82596_receive()
670 /* printf("Next Receive: rbd is %08x\n", rbd); */ in i82596_receive()
705 rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ in i82596_receive()
706 DBG(printf("Next Receive: rfd is %08x\n", rfd_p)); in i82596_receive()
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| H A D | spapr_llan.c | 109 RxBufPool *rx_pool[RX_MAX_POOLS]; /* Receive buffer descriptor pools */
120 * The last 8 bytes of the receive buffer list page (that has been
123 * suitable receive buffer available. This function is used to increase
135 * Get buffer descriptor from one of our receive buffer pools
168 * Get buffer descriptor from the receive buffer list page that has been
243 /* Update the receive queue */ in spapr_vlan_receive()
278 .receive = spapr_vlan_receive,
473 hcall_dprintf("Bad receive queue\n"); in h_register_logical_lan()
492 /* Initialize the receive queue */ in h_register_logical_lan()
556 * Enqueuing receive buffer by adding it to one of our receive buffer pools
[all …]
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| /qemu/qapi/ |
| H A D | virtio.json | 300 # "VIRTIO_NET_F_MRG_RXBUF: Driver can merge receive buffers"
311 # "VIRTIO_NET_F_MRG_RXBUF: Driver can merge receive buffers"
334 # "VIRTIO_NET_F_MRG_RXBUF: Driver can merge receive buffers",
335 # "VIRTIO_NET_F_HOST_UFO: Device can receive UFO",
336 # "VIRTIO_NET_F_HOST_ECN: Device can receive TSO with ECN",
337 # "VIRTIO_NET_F_HOST_TSO6: Device can receive TSOv6",
338 # "VIRTIO_NET_F_HOST_TSO4: Device can receive TSOv4",
339 # "VIRTIO_NET_F_GUEST_UFO: Driver can receive UFO",
340 # "VIRTIO_NET_F_GUEST_ECN: Driver can receive TSO with ECN",
341 # "VIRTIO_NET_F_GUEST_TSO6: Driver can receive TSOv6",
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| H A D | common.json | 167 # queue or receive queue or both.
169 # @all: the filter is attached both to the receive and the transmit
172 # @rx: the filter is attached to the receive queue of the netdev,
173 # where it will receive packets sent to the netdev.
176 # where it will receive packets sent by the netdev.
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| H A D | ebpf.json | 16 # Currently, there is a possible eBPF for receive-side scaling (RSS).
37 # @rss: Receive side scaling, technology that allows steering traffic
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| /qemu/include/standard-headers/linux/ |
| H A D | virtio_net.h | 48 #define VIRTIO_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */
56 #define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow
97 /* Maximum number of each of transmit and receive queues;
156 /* Receive Segment Coalescing */
293 * Control Receive Flow Steering
298 * enables Receive Flow Steering, specifying the number of the transmit and
299 * receive queues that will be used. After the command is consumed and acked by
300 * the device, the device will not steer new packets on receive virtqueues
316 * the receive steering to use a hash calculated for incoming packet
317 * to decide on receive virtqueue to place the packet. The command
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| /qemu/linux-user/mips/ |
| H A D | sockbits.h | 29 #define TARGET_SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band.
37 #define TARGET_SO_RCVBUF 0x1002 /* Receive buffer. */
39 #define TARGET_SO_RCVLOWAT 0x1004 /* receive low-water mark */
41 #define TARGET_SO_RCVTIMEO 0x1006 /* receive timeout */
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| /qemu/rust/hw/char/pl011/src/ |
| H A D | registers.rs | 26 /// Receive Status Register or Error Clear Register
76 /// Receive Status Register / Data Register common error bits
111 /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR`
113 /// This register provides a different way to read the four receive
164 /// RXFE: Receive FIFO empty
168 /// RXFF: Receive FIFO full
252 /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
295 /// `RXE` Receive enable
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| /qemu/hw/virtio/ |
| H A D | virtio-qmp.c | 261 "VIRTIO_NET_F_GUEST_TSO4: Driver can receive TSOv4"),
263 "VIRTIO_NET_F_GUEST_TSO6: Driver can receive TSOv6"),
265 "VIRTIO_NET_F_GUEST_ECN: Driver can receive TSO with ECN"),
267 "VIRTIO_NET_F_GUEST_UFO: Driver can receive UFO"),
269 "VIRTIO_NET_F_HOST_TSO4: Device can receive TSOv4"),
271 "VIRTIO_NET_F_HOST_TSO6: Device can receive TSOv6"),
273 "VIRTIO_NET_F_HOST_ECN: Device can receive TSO with ECN"),
275 "VIRTIO_NET_F_HOST_UFO: Device can receive UFO"),
277 "VIRTIO_NET_F_MRG_RXBUF: Driver can merge receive buffers"),
292 "VIRTIO_NET_F_MQ: Multiqueue with automatic receive steering "
[all …]
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| /qemu/pc-bios/s390-ccw/ |
| H A D | virtio-net.c | 31 #define VQ_RX 0 /* Receive queue */
45 static uint16_t rx_last_idx; /* Last index in receive queue "used" ring */
68 IPL_assert(buf != NULL, "Can not allocate memory for receive buffers"); in virtio_net_init()
112 puts("virtio-net: Receive buffer too small"); in recv()
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| /qemu/include/hw/hyperv/ |
| H A D | vmbus.h | 91 * A unit of work parsed out of a message in the receive (i.e. guest->host)
140 * Prepare to fetch a batch of packets from the receive ring buffer.
153 * Peek at the receive (i.e. guest->host) ring buffer and extract a unit of
172 * Propagate the private copy of the read index into the receive ring buffer,
175 * Return the number of bytes popped off the receive ring buffer by the
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| /qemu/include/chardev/ |
| H A D | char.h | 173 * front end cannot receive data at the moment. The function must be polled
176 * Returns: the number of bytes the front end can receive via @qemu_chr_be_write
182 * @buf: a buffer to receive data from the front end
183 * @len: the number of bytes to receive from the front end
193 * @buf: a buffer to receive data from the front end
194 * @len: the number of bytes to receive from the front end
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| /qemu/docs/ |
| H A D | colo-proxy.txt | 61 |guest receive | guest send
65 … tap | rx:receive packets sent to t…
66 … | tx:receive packets sent by t…
69 1.Guest receive packet route:
81 If receive packet is TCP packet,we will adjust ack
90 Redirect server filter receive primary guest packet
94 COLO-compare receive primary guest packet then
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| /qemu/net/ |
| H A D | filter-buffer.c | 49 * for the next filter or receiver to notify us that it can receive in filter_buffer_release_timer()
72 * FIXME: Even if the guest can't receive packets for some reasons, in filter_buffer_receive_iov()
75 * For some reason, receiver could not receive more packets in filter_buffer_receive_iov()
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| /qemu/include/hw/char/ |
| H A D | sifive_uart.h | 44 SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */
49 SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
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| /qemu/include/hw/i2c/ |
| H A D | smbus_master.h | 42 * to receive. Otherwise receive "len" bytes. If send_cmd is set, send
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| /qemu/include/system/ |
| H A D | spdm-socket.h | 38 * spdm_socket_rsp: send and receive a message to a SPDM server
46 * Send platform data to a SPDM server on socket and then receive
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| /qemu/hw/net/can/ |
| H A D | can_sja1000.c | 503 if (0x04 & val) { /* Release Receive Buffer */ in can_sja_mem_write()
607 if (0x04 & val) { /* Release Receive Buffer */ in can_sja_mem_write()
683 s->interrupt_pel |= (1 << 0); /* Receive interrupt. */ in can_sja_mem_read()
732 s->interrupt_bas |= (1 << 0); /* Receive interrupt. */ in can_sja_mem_read()
796 can_display_msg("[cansja]: receive ", frame); in can_sja_receive()
826 qemu_log("[cansja]: receive FIFO overrun\n"); in can_sja_receive()
834 qemu_log("[cansja]: message stored in receive FIFO\n"); in can_sja_receive()
842 s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */ in can_sja_receive()
867 qemu_log("[cansja]: receive FIFO overrun\n"); in can_sja_receive()
883 s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */ in can_sja_receive()
[all …]
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