Lines Matching full:receive

73 #define DMA_RCV_BASE_ADDR       0x000003c3   /* Receive List Base */
79 /* Receive Interrupt Watchdog Timer */
97 #define DMA_STATUS_RS_MASK      0x000e0000   /* Receive Process State */
101 #define DMA_STATUS_ERI          0x00004000   /* Early Receive Interrupt */
104 #define DMA_STATUS_RWT          0x00000200   /* Receive Watchdog Timeout */
105 #define DMA_STATUS_RPS          0x00000100   /* Receive Process Stopped */
106 #define DMA_STATUS_RU           0x00000080   /* Receive Buffer Unavailable */
107 #define DMA_STATUS_RI           0x00000040   /* Receive Interrupt */
109 #define DMA_STATUS_OVF          0x00000010   /* Receive Overflow */
117 #define DMA_CONTROL_SR          0x00000002   /* Start/Stop Receive */
388     .receive = eth_rx,