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/qemu/hw/net/
H A Dxilinx_axienet.c62 struct PHY { struct
67 unsigned int (*read)(struct PHY *phy, unsigned int req); argument
68 void (*write)(struct PHY *phy, unsigned int req, argument
72 static unsigned int tdk_read(struct PHY *phy, unsigned int req) in tdk_read() argument
81 if (!phy->link) { in tdk_read()
99 r |= phy->regs[4] & (15 << 5); in tdk_read()
104 /* Marvell PHY on many xilinx boards. */ in tdk_read()
113 if (!phy->link) { in tdk_read()
118 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); in tdk_read()
119 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); in tdk_read()
[all …]
H A De1000x_common.h78 e1000x_update_regs_on_link_down(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_link_down() argument
81 phy[MII_BMSR] &= ~MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_down()
82 phy[MII_BMSR] &= ~MII_BMSR_AN_COMP; in e1000x_update_regs_on_link_down()
83 phy[MII_ANLPAR] &= ~MII_ANLPAR_ACK; in e1000x_update_regs_on_link_down()
87 e1000x_update_regs_on_link_up(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_link_up() argument
90 phy[MII_BMSR] |= MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_up()
118 void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer);
123 void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy);
H A De1000_regs.h53 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
89 #define E1000_POEMB 0x00F10 /* PHY OEM Bits Register - RW */
128 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
129 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
191 /* PHY 1000 MII Register/Bit Definitions */
230 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
231 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
234 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
237 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
H A De1000x_common.c162 void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer) in e1000x_restart_autoneg() argument
164 e1000x_update_regs_on_link_down(mac, phy); in e1000x_restart_autoneg()
186 void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy) in e1000x_update_regs_on_autoneg_done() argument
188 e1000x_update_regs_on_link_up(mac, phy); in e1000x_update_regs_on_autoneg_done()
189 phy[MII_ANLPAR] |= MII_ANLPAR_ACK; in e1000x_update_regs_on_autoneg_done()
190 phy[MII_BMSR] |= MII_BMSR_AN_COMP; in e1000x_update_regs_on_autoneg_done()
H A Dtrace-events125 e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x"
126 e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED"
127 e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x"
128 e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED"
131 e1000e_core_ctrl_phy_reset(void) "Doing PHY reset"
274 igb_core_mdic_read(uint32_t addr, uint32_t data) "MDIC READ: PHY[%u] = 0x%x"
275 igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED"
276 igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x"
277 igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED"
417 tulip_mii_write(int phy, int reg, uint16_t data) "phy 0x%x reg 0x%x data 0x%04x"
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H A Dtulip.c428 /* Readonly mask for MDI (PHY) registers */
436 static uint16_t tulip_mii_read(TULIPState *s, int phy, int reg) in tulip_mii_read() argument
439 if (phy == 1) { in tulip_mii_read()
442 trace_tulip_mii_read(phy, reg, ret); in tulip_mii_read()
446 static void tulip_mii_write(TULIPState *s, int phy, int reg, uint16_t data) in tulip_mii_write() argument
448 trace_tulip_mii_write(phy, reg, data); in tulip_mii_write()
450 if (phy != 1) { in tulip_mii_write()
462 int op, phy, reg; in tulip_mii() local
493 phy = (s->mii_word >> 7) & 0x1f; in tulip_mii()
497 s->mii_word = tulip_mii_read(s, phy, reg); in tulip_mii()
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H A Dimx_fec.c223 * The MII phy could raise a GPIO to the processor which in turn
226 * have to poll for the PHY status.
241 uint32_t phy = reg / 32; in imx_phy_read() local
247 if (phy != s->phy_num) { in imx_phy_read()
248 if (s->phy_consumer && phy == s->phy_consumer->phy_num) { in imx_phy_read()
251 trace_imx_phy_read_num(phy, s->phy_num); in imx_phy_read()
263 uint32_t phy = reg / 32; in imx_phy_write() local
269 if (phy != s->phy_num) { in imx_phy_write()
270 if (s->phy_consumer && phy == s->phy_consumer->phy_num) { in imx_phy_write()
273 trace_imx_phy_write_num(phy, s->phy_num); in imx_phy_write()
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H A Deepro100.c37 * * PHY emulation should be separated from nic emulation.
38 * Most nic emulations could share the same phy code.
312 /* Default values for MDI (PHY) registers */
323 /* Readonly mask for MDI (PHY) registers */
1134 "PHY Identification (Word 1)",
1135 "PHY Identification (Word 2)",
1161 uint8_t phy = (val & BITS(25, 21)) >> 21; in eepro100_read_mdi() local
1167 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", in eepro100_read_mdi()
1168 val, raiseint, mdi_op_name[opcode], phy, in eepro100_read_mdi()
1178 uint8_t phy = (val & BITS(25, 21)) >> 21; in eepro100_write_mdi() local
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H A De1000e_core.c649 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || in e1000e_tx_pkt_send()
1738 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; in e1000e_have_autoneg()
1744 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { in e1000e_update_flowctl_status()
1755 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_link_down()
1763 core->phy[0][MII_BMCR] = val & ~(0x3f | in e1000e_set_phy_ctrl()
1769 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_ctrl()
1776 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); in e1000e_set_phy_oem_bits()
1779 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_oem_bits()
1786 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; in e1000e_set_phy_page()
1798 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_core_set_link_status()
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/qemu/hw/net/fsl_etsec/
H A Dmiim.c34 uint8_t phy; in miim_read_cycle() local
38 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_read_cycle()
39 (void)phy; /* Unreferenced */ in miim_read_cycle()
58 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_read_cycle()
66 uint8_t phy; in miim_write_cycle() local
70 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; in miim_write_cycle()
71 (void)phy; /* Unreferenced */ in miim_write_cycle()
76 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); in miim_write_cycle()
/qemu/include/hw/misc/
H A Daspeed_sdmc.h25 * - PHY status regs at offset 0x400, length 0x200
26 * - PHY setting regs at offset 0x100, length 0x300
30 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
/qemu/hw/usb/
H A Dimx-usb-phy.c2 * i.MX USB PHY
9 * We need to implement basic reset control in the PHY control register.
14 #include "hw/usb/imx-usb-phy.h"
98 "%s: Read from non-existing USB PHY register 0x%" in imx_usbphy_read()
182 "%s: Write to %s USB PHY register 0x%" in imx_usbphy_write()
223 dc->desc = "i.MX USB PHY Module"; in imx_usbphy_class_init()
/qemu/hw/arm/
H A Dmcimx6ul-evk.c43 object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal); in mcimx6ul_evk_init()
44 object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal); in mcimx6ul_evk_init()
45 object_property_set_bool(OBJECT(s), "fec1-phy-connected", false, in mcimx6ul_evk_init()
H A Dfsl-imx7.c425 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", in fsl_imx7_realize()
432 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", in fsl_imx7_realize()
443 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", in fsl_imx7_realize()
672 * PCIe PHY in fsl_imx7_realize()
674 create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, in fsl_imx7_realize()
743 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
744 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
745 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0],
747 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1],
H A Dfsl-imx6ul.c23 #include "hw/usb/imx-usb-phy.h"
439 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", in fsl_imx6ul_realize()
446 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", in fsl_imx6ul_realize()
467 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", in fsl_imx6ul_realize()
710 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
711 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
712 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
714 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
H A Dsabrelite.c55 /* Ethernet PHY address is 6 */ in sabrelite_init()
56 object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); in sabrelite_init()
H A Dcubieboard.c59 if (!object_property_set_int(OBJECT(&a10->emac), "phy-addr", 1, &err)) { in cubieboard_init()
60 error_reportf_err(err, "Couldn't set phy address: "); in cubieboard_init()
H A Dfsl-imx6.c26 #include "hw/usb/imx-usb-phy.h"
382 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, in fsl_imx6_realize()
447 * PCIe PHY in fsl_imx6_realize()
449 create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR, in fsl_imx6_realize()
484 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
/qemu/include/hw/net/
H A Dcadence_gem.h77 /* PHY address */
79 /* PHY registers backing store */
82 uint8_t phy_loop; /* Are we in phy loopback? */
H A Dlan9118_phy.h2 * SMSC LAN9118 PHY emulation
17 #define TYPE_LAN9118_PHY "lan9118-phy"
/qemu/include/hw/pci-host/
H A Dfsl_imx8m_phy.h2 * i.MX8 PCIe PHY emulation
16 #define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy"
/qemu/include/standard-headers/linux/
H A Dethtool.h52 * @phy_address: MDIO address of PHY (transceiver); 0 or 255 if not
55 * PHY types, but not in a consistent way. Deprecated.
137 /* Device supports clause 22 register access to PHY or peripherals
144 /* Device supports clause 45 register access to PHY or peripherals
265 * 0 = lowest time supported by the PHY
272 * the PHY's RX & TX blocks are put into a low-power mode when there is no
274 * link-detection is available, and for TX the PHY wakes up to send link pulses
275 * to avoid any lock-ups in case the peer PHY may also be running in EDPD mode.
298 * Add your fresh new phy tunable attribute above and remember to update
671 * @ETH_SS_PHY_TUNABLES: PHY tunable names
[all …]
/qemu/hw/pci-host/
H A Dfsl_imx8m_phy.c2 * i.MX8 PCIe PHY emulation
69 .name = "fsl-imx8m-pcie-phy",
/qemu/hw/ide/
H A Dahci-internal.h98 AHCI_PORT_REG_SCR_STAT = 10, /* PxSSTS: SATA phy register: SStatus */
99 AHCI_PORT_REG_SCR_CTL = 11, /* PxSCTL: SATA phy register: SControl */
100 AHCI_PORT_REG_SCR_ERR = 12, /* PxSERR: SATA phy register: SError */
101 AHCI_PORT_REG_SCR_ACT = 13, /* PxSACT: SATA phy register: SActive */
103 AHCI_PORT_REG_SCR_NOTIF = 15, /* PxSNTF: SATA phy register: SNotification */
/qemu/pc-bios/
HDu-boot.e500 ... %s @ %08lx , seq %d phy-mode set_dir_flags get_value set_value Virtual root driver already exists ...

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