649     if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) ||  in e1000e_tx_pkt_send()
1738     return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN;  in e1000e_have_autoneg()
1744         core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) {  in e1000e_update_flowctl_status()
1755     e1000x_update_regs_on_link_down(core->mac, core->phy[0]);  in e1000e_link_down()
1763     core->phy[0][MII_BMCR] = val & ~(0x3f |  in e1000e_set_phy_ctrl()
1769         e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);  in e1000e_set_phy_ctrl()
1776     core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);  in e1000e_set_phy_oem_bits()
1779         e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);  in e1000e_set_phy_oem_bits()
1786     core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;  in e1000e_set_phy_page()
1798         e1000x_update_regs_on_link_down(core->mac, core->phy[0]);  in e1000e_core_set_link_status()
1801             !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {  in e1000e_core_set_link_status()
1802             e1000x_restart_autoneg(core->mac, core->phy[0],  in e1000e_core_set_link_status()
1805             e1000x_update_regs_on_link_up(core->mac, core->phy[0]);  in e1000e_core_set_link_status()
2188         e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);  in e1000e_autoneg_timer()
2258                                                     : core->phy[0][PHY_PAGE];  in e1000e_phy_reg_check_cap()
2277         core->phy[page][addr] = data;  in e1000e_phy_reg_write()
2288     if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */  in e1000e_set_mdic()
2295             val = (val ^ data) | core->phy[page][addr];  in e1000e_set_mdic()
3313         !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {  in e1000e_autoneg_resume()
3459     memset(core->phy, 0, sizeof core->phy);  in e1000e_reset()
3460     memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);  in e1000e_reset()
3502         core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP;  in e1000e_core_pre_save()