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/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
17 see 'PCIE-PCI bridge hot-plug' section),
25 PCIE-PCI bridge hot-plug
27 Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug.
36 that is planned to have PCIE-PCI bridge hot-plugged in.
62 At the moment this capability is used only in QEMU generic PCIe root port
63 (-device pcie-root-port). Capability construction function takes all reservation
73 -device pcie-root-port,bus=pcie.0,id=rp1,slot=1 \
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H A Dpcie.txt6 The doc proposes best practices on how to use PCI Express (PCIe) / PCI
10 Note that the PCIe features are available only when using the 'q35'
12 Other machine types do not use PCIe at this time.
37 2.1 Root Bus (pcie.0)
51 (2) PCI Express Root Ports (pcie-root-port), for starting exclusively
54 (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI
57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
60 pcie.0 bus
64 | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie |
67 2.1.1 To plug a device into pcie.0 as a Root Complex Integrated Endpoint use:
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H A Dbypass-iommu.txt31 qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
42 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
43 -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
55 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3 \
56 -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x4,bypass_iommu=true \
/qemu/docs/config/
H A Dq35-virtio-serial.cfg79 [device "pcie.1"]
80 driver = "pcie-root-port"
81 bus = "pcie.0"
87 [device "pcie.2"]
88 driver = "pcie-root-port"
89 bus = "pcie.0"
94 [device "pcie.3"]
95 driver = "pcie-root-port"
96 bus = "pcie.0"
101 [device "pcie.4"]
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H A Dq35-virtio-graphical.cfg74 [device "pcie.1"]
75 driver = "pcie-root-port"
76 bus = "pcie.0"
82 [device "pcie.2"]
83 driver = "pcie-root-port"
84 bus = "pcie.0"
89 [device "pcie.3"]
90 driver = "pcie-root-port"
91 bus = "pcie.0"
96 [device "pcie.4"]
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H A Dmach-virt-serial.cfg129 [device "pcie.1"]
130 driver = "pcie-root-port"
131 bus = "pcie.0"
137 [device "pcie.2"]
138 driver = "pcie-root-port"
139 bus = "pcie.0"
144 [device "pcie.3"]
145 driver = "pcie-root-port"
146 bus = "pcie.0"
151 [device "pcie.4"]
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H A Dmach-virt-graphical.cfg123 [device "pcie.1"]
124 driver = "pcie-root-port"
125 bus = "pcie.0"
131 [device "pcie.2"]
132 driver = "pcie-root-port"
133 bus = "pcie.0"
138 [device "pcie.3"]
139 driver = "pcie-root-port"
140 bus = "pcie.0"
145 [device "pcie.4"]
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H A Dq35-emulated.cfg79 [device "ich9-pcie-port-1"]
82 bus = "pcie.0"
87 [device "ich9-pcie-port-2"]
90 bus = "pcie.0"
95 [device "ich9-pcie-port-3"]
98 bus = "pcie.0"
103 [device "ich9-pcie-port-4"]
106 bus = "pcie.0"
122 bus = "pcie.0"
172 bus = "pcie.0"
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/qemu/tests/qtest/
H A Dreadconfig-test.c309 { "ich9-pcie-port-1", "ioh3420" }, in test_docs_q35_emulated()
310 { "ich9-pcie-port-2", "ioh3420" }, in test_docs_q35_emulated()
311 { "ich9-pcie-port-3", "ioh3420" }, in test_docs_q35_emulated()
312 { "ich9-pcie-port-4", "ioh3420" }, in test_docs_q35_emulated()
337 { "pcie.1", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
338 { "pcie.2", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
339 { "pcie.3", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
340 { "pcie.4", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
341 { "pcie.5", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
342 { "pcie.6", "pcie-root-port" }, in test_docs_q35_virtio_graphical()
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H A Dbios-tables-test.c1140 " -device pci-testdev,bus=pcie.0" in test_acpi_q35_tcg_bridge()
1155 " -device pci-testdev,bus=pcie.0,acpi-index=101,addr=3.0" in test_acpi_q35_tcg_no_acpi_hotplug()
1160 " -device pcie-root-port,id=hprp,port=0x0,chassis=1,addr=6.0" in test_acpi_q35_tcg_no_acpi_hotplug()
1162 " -device pcie-root-port,id=nohprp,port=0x0,chassis=2,hotplug=off," in test_acpi_q35_tcg_no_acpi_hotplug()
1165 " -device pcie-root-port,id=nohprpint,port=0x0,chassis=3,hotplug=off," in test_acpi_q35_tcg_no_acpi_hotplug()
1168 " -device pcie-root-port,id=hprp2,port=0x0,chassis=4,bus=nohprpint," in test_acpi_q35_tcg_no_acpi_hotplug()
1184 " -device pcie-root-port,id=rp0,multifunction=on," in test_acpi_q35_multif_bridge()
1186 " -device pcie-root-port,id=rp1,port=0x1,chassis=2,addr=0x3.0x1" in test_acpi_q35_multif_bridge()
1187 " -device pcie-root-port,id=rp2,port=0x0,chassis=3,bus=rp1,addr=0.0" in test_acpi_q35_multif_bridge()
1189 " -device pcie-root-port,id=rphptgt1,port=0x0,chassis=5,addr=2.1" in test_acpi_q35_multif_bridge()
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H A Ddrive_del-test.c295 "-machine q35 -device pcie-root-port,id=p1 " in test_cli_device_del_q35()
296 "-device pcie-pci-bridge,bus=p1,id=b1 " in test_cli_device_del_q35()
382 qts = qtest_initf("-machine q35 -device pcie-root-port,id=p1 " in test_device_add_and_del_q35()
383 "-device pcie-pci-bridge,bus=p1,id=b1 " in test_device_add_and_del_q35()
432 qts = qtest_init("-machine q35 -device pcie-root-port,id=p1 " in test_drive_add_device_add_and_del_q35()
433 "-device pcie-pci-bridge,bus=p1,id=b1"); in test_drive_add_device_add_and_del_q35()
485 qts = qtest_init("-machine q35 -device pcie-root-port,id=p1 " in test_blockdev_add_device_add_and_del_q35()
486 "-device pcie-pci-bridge,bus=p1,id=b1"); in test_blockdev_add_device_add_and_del_q35()
/qemu/docs/system/ppc/
H A Dpowernv.rst23 * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
36 * EEH support for PCIe Host bridge controllers.
79 -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0 \
89 -device ich9-ahci,id=sata0,bus=pcie.1,addr=0x0 \
93 Complex PCIe configuration
98 on any of the available PCIe slots using command line options such as:
102 -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
105 -device megasas,id=scsi0,bus=pcie.0,addr=0x0
117 -device megasas,id=scsi0,bus=pcie.0,addr=0x0 \
121 -device pcie-pci-bridge,id=bridge1,bus=pcie.1,addr=0x0 \
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/qemu/docs/specs/
H A Dpci-ids.rst78 PCIe host bridge
84 PCIe Expander Bridge (``-device pxb-pcie``)
86 PCIe Root Port (``-device pcie-root-port``)
90 PCIe-to-PCI bridge (``-device pcie-pci-bridge``)
94 PCIe NVMe device (``-device nvme``)
/qemu/include/hw/i386/
H A Dmicrovm.h45 * 12 | ps2 | pcie
46 * 13 | fpu | pcie
47 * 14 | ide 0 | pcie
48 * 15 | ide 1 | pcie
71 #define MICROVM_MACHINE_PCIE "pcie"
90 OnOffAuto pcie; member
/qemu/include/hw/pci-host/
H A Ddesignware.h4 * Designware PCIe IP block emulation
28 #define TYPE_DESIGNWARE_PCIE_ROOT_BUS "designware-pcie-root-BUS"
31 #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
34 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
H A Dxilinx-pcie.h2 * Xilinx PCIe host controller emulation.
28 #define TYPE_XILINX_PCIE_HOST "xilinx-pcie-host"
31 #define TYPE_XILINX_PCIE_ROOT "xilinx-pcie-root"
H A Dfsl_imx8m_phy.h2 * i.MX8 PCIe PHY emulation
16 #define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy"
/qemu/hw/pci-host/
H A Ddesignware.c4 * Designware PCIe IP block emulation
150 * PCIE lane (which in our case is irrelevant) and doesn't in designware_pcie_root_config_read()
405 br->bus_name = "dw-pcie"; in designware_pcie_root_realize()
502 root, "pcie-msi", 0x4); in designware_pcie_root_realize()
527 .name = "designware-pcie-msi-bank",
539 .name = "designware-pcie-msi",
555 .name = "designware-pcie-viewport",
568 .name = "designware-pcie-root",
685 "pcie.reg", 4 * 1024); in designware_pcie_host_realize()
688 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); in designware_pcie_host_realize()
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/qemu/hw/arm/
H A Dfsl-imx6.c108 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); in fsl_imx6_init()
423 * PCIe in fsl_imx6_realize()
425 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); in fsl_imx6_realize()
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); in fsl_imx6_realize()
436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); in fsl_imx6_realize()
438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); in fsl_imx6_realize()
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); in fsl_imx6_realize()
442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); in fsl_imx6_realize()
444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); in fsl_imx6_realize()
447 * PCIe PHY in fsl_imx6_realize()
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H A Dfsl-imx7.c150 * PCIE in fsl_imx7_init()
152 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); in fsl_imx7_init()
589 * PCIE in fsl_imx7_realize()
591 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); in fsl_imx7_realize()
592 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); in fsl_imx7_realize()
602 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); in fsl_imx7_realize()
604 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); in fsl_imx7_realize()
606 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); in fsl_imx7_realize()
608 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); in fsl_imx7_realize()
610 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); in fsl_imx7_realize()
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/qemu/hw/pci-bridge/
H A Dpci_expander_bridge.c30 enum BusType { PCI, PCIE, CXL }; enumerator
37 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
52 #define TYPE_PXB_PCIE_DEV "pxb-pcie"
179 /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ in pxb_host_class_init()
235 /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */ in pxb_cxl_host_class_init()
359 if (type == PCIE) { in pxb_dev_realize_common()
409 error_setg(errp, "pxb devices cannot reside on a PCIe bus"); in pxb_dev_realize()
461 error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus"); in pxb_pcie_dev_realize()
465 pxb_dev_realize_common(dev, PCIE, errp); in pxb_pcie_dev_realize()
497 /* A CXL PXB's parent bus is still PCIe */ in pxb_cxl_dev_realize()
/qemu/docs/system/devices/
H A Dcxl.rst20 CXL elements are built upon an equivalent PCIe devices.
24 * Most conventional PCIe interfaces
96 A CXL host bridge is similar to the PCIe equivalent, but with a
114 A CXL Root Port serves the same purpose as a PCIe Root Port.
116 Extended Capabilities (DVSEC) in PCIe Configuration Space
128 A CXL switch has a similar architecture to those in PCIe,
309 -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
319 -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
330 -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
349 -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
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/qemu/hw/i386/
H A Dmicrovm.c116 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", in create_gpex()
129 memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg, in create_gpex()
136 memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg, in create_gpex()
230 if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) { in microvm_devices_init()
542 OnOffAuto pcie = mms->pcie; in microvm_machine_get_pcie() local
544 visit_type_OnOffAuto(v, name, &pcie, errp); in microvm_machine_get_pcie()
552 visit_type_OnOffAuto(v, name, &mms->pcie, errp); in microvm_machine_set_pcie()
623 mms->pcie = ON_OFF_AUTO_AUTO; in microvm_machine_initfn()
632 * pcie host bridge (gpex) on microvm has no io address window,
635 { "pcie-root-port", "io-reserve", "0" },
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/qemu/include/hw/pci/
H A Dpcie_port.h29 #define TYPE_PCIE_PORT "pcie-port"
47 #define TYPE_PCIE_SLOT "pcie-slot"
78 #define TYPE_PCIE_ROOT_PORT "pcie-root-port-base"
/qemu/tests/qemu-iotests/tests/
H A Dnbd-tls-iothread100 -device '{"driver":"pcie-root-port", "id":"root0", "multifunction":true,
101 "bus":"pcie.0"}' \
120 -device '{"driver":"pcie-root-port", "id":"root0", "multifunction":true,
121 "bus":"pcie.0"}' \

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