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/qemu/hw/net/
H A Dallwinner_emac.c34 static void mii_set_link(RTL8201CPState *mii, bool link_ok) in mii_set_link() argument
37 mii->bmsr |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; in mii_set_link()
38 mii->anlpar |= MII_ANAR_TXFD | MII_ANAR_10FD | MII_ANAR_10 | in mii_set_link()
41 mii->bmsr &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in mii_set_link()
42 mii->anlpar = MII_ANAR_TX; in mii_set_link()
46 static void mii_reset(RTL8201CPState *mii, bool link_ok) in mii_reset() argument
48 mii->bmcr = MII_BMCR_FD | MII_BMCR_AUTOEN | MII_BMCR_SPEED; in mii_reset()
49 mii->bmsr = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | in mii_reset()
51 mii->anar = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | in mii_reset()
53 mii->anlpar = MII_ANAR_TX; in mii_reset()
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H A Dopencores_eth.c36 #include "hw/net/mii.h"
60 /* PHY MII registers */
65 typedef struct Mii { struct
68 } Mii; argument
70 static void mii_set_link(Mii *s, bool link_ok) in mii_set_link()
83 static void mii_reset(Mii *s) in mii_reset()
97 static void mii_ro(Mii *s, uint16_t v) in mii_ro()
101 static void mii_write_bmcr(Mii *s, uint16_t v) in mii_write_bmcr()
110 static void mii_write_host(Mii *s, unsigned idx, uint16_t v) in mii_write_host()
112 static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = { in mii_write_host()
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H A Dxilinx_axienet.c336 /* MII regs. */
345 } mii; member
467 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ in enet_read()
496 r = s->mii.regs[addr & 3]; in enet_read()
569 /* Enable the MII. */ in enet_write()
576 s->mii.mc = value; in enet_write()
587 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); in enet_write()
589 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); in enet_write()
594 s->mii.mcr = value; in enet_write()
600 s->mii.regs[addr & 3] = value; in enet_write()
H A Dlan9118.c224 Lan9118PhyState mii; member
387 lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, in lan9118_set_link()
643 if (s->mii.control & 0x4000) { in do_tx_packet()
832 lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); in do_mac_write()
834 s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); in do_mac_write()
1029 lan9118_phy_reset(&s->mii); in lan9118_writel()
1277 object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); in lan9118_realize()
1278 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { in lan9118_realize()
1281 qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); in lan9118_realize()
H A Dimx_fec.c223 * The MII phy could raise a GPIO to the processor which in turn
235 lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, in imx_eth_set_link()
258 return lan9118_phy_read(&s->mii, reg); in imx_phy_read()
280 lan9118_phy_write(&s->mii, reg, val); in imx_phy_write()
1209 object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); in imx_eth_realize()
1210 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { in imx_eth_realize()
1213 qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); in imx_eth_realize()
H A Dtrace-events4 allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " valu…
5 allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=…
37 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
38 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
348 sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x …
349 sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x va…
350 sungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32
351 sungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x"
H A Dallwinner-sun8i-emac.c193 /* MII register offsets */
203 /* MII register flags */
237 /* MII constants */
301 "unknown MII register 0x%x\n", reg); in allwinner_sun8i_emac_mii_cmd()
328 "unknown MII register 0x%x\n", reg); in allwinner_sun8i_emac_mii_cmd()
H A Dftgmac100.c23 #include "hw/net/mii.h"
227 * Specific RTL8211E MII Registers
273 * The MII phy could raise a GPIO to the processor which in turn
1283 * AST2600 MII controller
1429 dc->desc = "Aspeed MII controller"; in aspeed_mii_class_init()
H A Dlan9118_phy.c17 #include "hw/net/mii.h"
H A Digbvf.c42 #include "hw/net/mii.h"
H A De1000x_common.c27 #include "hw/net/mii.h"
H A Dmv88w8618_eth.c37 /* MII PHY access */
H A Dnpcm7xx_emc.c20 * - MII is not implemented, MIIDA.BUSY and MIID always return zero
632 * We don't implement MII. For determinism, always return zero as in npcm7xx_emc_read()
/qemu/include/hw/net/
H A Dmii.h2 * Common network MII address and register definitions.
52 #define MII_BMCR_ISOLATE (1 << 10) /* Isolate data paths from MII */
66 #define MII_BMSR_MFPS (1 << 6) /* MII Frame Preamble Suppression */
H A Dallwinner_emac.h29 #include "hw/net/mii.h"
157 RTL8201CPState mii; member
H A Dftgmac100.h81 * AST2600 MII controller
H A Dallwinner-sun8i-emac.h64 * @name Media Independent Interface (MII)
H A Dimx_fec.h269 Lan9118PhyState mii; member
/qemu/hw/net/fsl_etsec/
H A Dregisters.c119 {0x520, "MIIMCFG", "MII management configuration", ACC_RW, 0x00000007},
120 {0x524, "MIIMCOM", "MII management command", ACC_RW, 0x00000000},
121 {0x528, "MIIMADD", "MII management address", ACC_RW, 0x00000000},
122 {0x52C, "MIIMCON", "MII management control", ACC_WO, 0x00000000},
123 {0x530, "MIIMSTAT", "MII management status", ACC_RO, 0x00000000},
124 {0x534, "MIIMIND", "MII management indicator", ACC_RO, 0x00000000},
H A Dmiim.c26 #include "hw/net/mii.h"
/qemu/hw/arm/
H A Daspeed_ast2600.c223 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); in aspeed_soc_ast2600_init()
520 object_property_set_link(OBJECT(&s->mii[i]), "nic", in aspeed_soc_ast2600_realize()
522 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { in aspeed_soc_ast2600_realize()
526 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, in aspeed_soc_ast2600_realize()
H A Daspeed_ast27x0.c479 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); in aspeed_soc_ast2700_init()
806 object_property_set_link(OBJECT(&s->mii[i]), "nic", in aspeed_soc_ast2700_realize()
808 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { in aspeed_soc_ast2700_realize()
812 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, in aspeed_soc_ast2700_realize()
/qemu/include/hw/arm/
H A Daspeed_soc.h84 AspeedMiiState mii[ASPEED_MACS_NUM]; member
/qemu/tests/qtest/libqos/
H A Digb.c22 #include "hw/net/mii.h"
/qemu/include/standard-headers/linux/
H A Dethtool.h138 * using the interface defined in "standard-headers/linux/mii.h". This should not be
145 * using the interface defined in "standard-headers/linux/mii.h" and <linux/mdio.h>.
2101 #define SUPPORTED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII)
2141 #define ADVERTISED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII)
2233 * MII or SGMII).
2574 * is connected to, as in what is on the other end of the MII bus. Most PHYs
2577 * MII interface as its output.

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