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/qemu/docs/system/arm/
H A Dmps2.rst1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
6 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
10 Since the CPU itself and most of the devices are in the FPGA, the
12 FPGA image.
14 QEMU models the following FPGA images:
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
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H A Demcraft-sf2.rst1 Emcraft SmartFusion2 SOM kit (``emcraft-sf2``)
4 The ``emcraft-sf2`` board emulates the SmartFusion2 SOM kit from
5 Emcraft (M2S010). This is a System-on-Module from EmCraft systems,
6 based on the SmartFusion2 SoC FPGA from Microsemi Corporation.
7 The SoC is based on a Cortex-M4 processor.
11 - System timer
12 - System registers
13 - SPI controller
14 - UART
15 - EMAC
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
7 FPGA logic (PL) and an Artificial Intelligence Engine (AIE).
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
30 - 8 ADMA (Xilinx zDMA) channels
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/qemu/hw/arm/
H A Dmps3r.c2 * Arm MPS3 board emulation for Cortex-R-based FPGA images.
3 * (For M-profile images see mps2.c and mps2tz.c.)
14 * The MPS3 is an FPGA based dev board. This file handles FPGA images
15 * which use the Cortex-R CPUs. We model these separately from the
16 * M-profile images, because on M-profile the FPGA image is based on
18 * the R-profile FPGA images don't have that abstraction layer.
20 * We model the following FPGA images here:
21 * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
31 #include "system/address-spaces.h"
35 #include "hw/or-irq.h"
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H A Dmps2.c12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
23 * Notes which document the FPGA images can be found here:
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H A Dmps2-tz.c2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
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/qemu/docs/system/riscv/
H A Dshakti-c.rst4 Shakti C Reference Platform is a reference platform based on arty a7 100t
7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
13 For more info on the Shakti C-class core, please see:
14 https://c-class.readthedocs.io/en/latest/
17 -----------------
21 * 1 C-class core
23 * Platform-Level Interrupt Controller (PLIC)
27 ------------
29 The ``shakti_c`` machine can start using the standard -bios
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/qemu/hw/misc/
H A Dzynq_slcr.c6 * Based on hw/arm_sysctl.c, written by Paul Brook
25 #include "hw/qdev-clock.h"
27 #include "hw/qdev-properties.h"
89 REG32(FPGA ## n ## _CLK_CTRL, (start)) \
90 REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
91 REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\
92 REG32(FPGA ## n ## _THR_STA, (start) + 0xc)
188 #define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr"
229 /* frequency multiplier -> period division */ in zynq_slcr_compute_pll()
260 * "The 6-bit divider provides a divide range of 1 to 63" in zynq_slcr_compute_clock()
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/qemu/hw/pci-host/
H A Dversatile.c4 * Copyright (c) 2006-2009 CodeSourcery.
18 #include "hw/qdev-properties.h"
59 * -------------------------------
116 if (s->realview) { in pci_vpb_update_window()
120 offset = s->imap[i] & ~(s->mem_win_size[i] - 1); in pci_vpb_update_window()
123 offset = s->imap[i] << 28; in pci_vpb_update_window()
125 memory_region_set_alias_offset(&s->pci_mem_window[i], offset); in pci_vpb_update_window()
130 /* Update all alias windows based on the current register state */ in pci_vpb_update_all_windows()
146 .name = "versatile-pci",
189 int win = (addr - PCI_IMAP0) >> 2; in pci_vpb_reg_write()
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H A Dbonito.c4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
9 * Contributions after 2012-01-13 are licensed under the terms of the
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
25 * pci slot = 17-12=5
44 #include "qemu/error-report.h"
48 #include "hw/pci-host/bonito.h"
65 /* from linux source code. include/asm-mips/mips-boards/bonito64.h*/
68 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
71 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
74 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
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