Lines Matching +full:fpga +full:- +full:based
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
34 #include "hw/or-irq.h"
36 #include "system/address-spaces.h"
38 #include "hw/qdev-properties.h"
40 #include "hw/char/cmsdk-apb-uart.h"
41 #include "hw/timer/cmsdk-apb-timer.h"
42 #include "hw/timer/cmsdk-apb-dualtimer.h"
43 #include "hw/misc/mps2-scc.h"
44 #include "hw/misc/mps2-fpgaio.h"
49 #include "hw/watchdog/cmsdk-apb-watchdog.h"
50 #include "hw/qdev-clock.h"
83 /* FPGA APB subsystem */
95 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
96 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
97 #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
98 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
109 * pre-existing behaviour that used to be hardcoded in the in OBJECT_DECLARE_TYPE()
145 if (machine->ram_size != mc->default_ram_size) { in mps2_common_init()
146 char *sz = size_to_str(mc->default_ram_size); in mps2_common_init()
152 /* This clock doesn't need migration because it is fixed-frequency */ in mps2_common_init()
153 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); in mps2_common_init()
154 clock_set_hz(mms->sysclk, SYSCLK_FRQ); in mps2_common_init()
156 mms->refclk = clock_new(OBJECT(machine), "REFCLK"); in mps2_common_init()
157 clock_set_hz(mms->refclk, REFCLK_FRQ); in mps2_common_init()
159 /* The FPGA images have an odd combination of different RAMs, in mps2_common_init()
178 * 0x00000000 .. 0x0003ffff : FPGA block RAM in mps2_common_init()
190 memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram); in mps2_common_init()
192 if (mmc->has_block_ram) { in mps2_common_init()
193 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); in mps2_common_init()
194 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", in mps2_common_init()
195 &mms->blockram, 0x01004000); in mps2_common_init()
196 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", in mps2_common_init()
197 &mms->blockram, 0x01008000); in mps2_common_init()
198 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", in mps2_common_init()
199 &mms->blockram, 0x0100c000); in mps2_common_init()
202 switch (mmc->fpga_type) { in mps2_common_init()
206 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); in mps2_common_init()
207 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); in mps2_common_init()
208 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); in mps2_common_init()
209 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", in mps2_common_init()
210 &mms->ssram23, 0x20400000); in mps2_common_init()
213 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); in mps2_common_init()
214 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); in mps2_common_init()
215 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); in mps2_common_init()
216 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); in mps2_common_init()
222 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); in mps2_common_init()
223 armv7m = DEVICE(&mms->armv7m); in mps2_common_init()
224 switch (mmc->fpga_type) { in mps2_common_init()
227 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
230 /* The AN500 configures its Cortex-M7 with 16 MPU regions */ in mps2_common_init()
231 qdev_prop_set_uint32(armv7m, "mpu-ns-regions", 16); in mps2_common_init()
232 qdev_prop_set_uint32(armv7m, "num-irq", 32); in mps2_common_init()
235 qdev_prop_set_uint32(armv7m, "num-irq", 64); in mps2_common_init()
240 qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); in mps2_common_init()
241 qdev_connect_clock_in(armv7m, "refclk", mms->refclk); in mps2_common_init()
242 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); in mps2_common_init()
243 qdev_prop_set_bit(armv7m, "enable-bitband", true); in mps2_common_init()
244 object_property_set_link(OBJECT(&mms->armv7m), "memory", in mps2_common_init()
246 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); in mps2_common_init()
256 * over the unimplemented-region mapping). in mps2_common_init()
268 switch (mmc->fpga_type) { in mps2_common_init()
280 object_property_set_int(orgate, "num-lines", 6, &error_fatal); in mps2_common_init()
304 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
323 object_property_set_int(orgate, "num-lines", 10, &error_fatal); in mps2_common_init()
339 object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); in mps2_common_init()
348 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
364 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); in mps2_common_init()
368 for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { in mps2_common_init()
374 object_initialize_child(OBJECT(mms), name, &mms->timer[i], in mps2_common_init()
376 sbd = SYS_BUS_DEVICE(&mms->timer[i]); in mps2_common_init()
377 qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); in mps2_common_init()
383 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, in mps2_common_init()
385 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); in mps2_common_init()
386 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); in mps2_common_init()
387 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, in mps2_common_init()
389 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); in mps2_common_init()
390 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, in mps2_common_init()
392 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); in mps2_common_init()
393 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); in mps2_common_init()
394 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, in mps2_common_init()
396 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); in mps2_common_init()
398 /* FPGA APB subsystem */ in mps2_common_init()
399 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); in mps2_common_init()
400 sccdev = DEVICE(&mms->scc); in mps2_common_init()
401 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); in mps2_common_init()
402 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); in mps2_common_init()
403 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); in mps2_common_init()
404 /* All these FPGA images have the same OSCCLK configuration */ in mps2_common_init()
411 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); in mps2_common_init()
414 &mms->fpgaio, TYPE_MPS2_FPGAIO); in mps2_common_init()
415 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); in mps2_common_init()
416 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); in mps2_common_init()
417 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); in mps2_common_init()
431 object_property_set_int(orgate, "num-lines", 2, &error_fatal); in mps2_common_init()
451 * internal-only bus: mark it full to avoid user-created in mps2_common_init()
461 * except that it doesn't support the checksum-offload feature. in mps2_common_init()
463 lan9118_init(mmc->ethernet_base, in mps2_common_init()
465 mmc->fpga_type == FPGA_AN511 ? 47 : 13)); in mps2_common_init()
467 armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename, in mps2_common_init()
475 mc->init = mps2_common_init; in mps2_class_init()
476 mc->max_cpus = 1; in mps2_class_init()
477 mc->default_ram_size = 16 * MiB; in mps2_class_init()
478 mc->default_ram_id = "mps.ram"; in mps2_class_init()
486 ARM_CPU_TYPE_NAME("cortex-m3"), in mps2_an385_class_init()
490 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; in mps2_an385_class_init()
491 mmc->fpga_type = FPGA_AN385; in mps2_an385_class_init()
492 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in mps2_an385_class_init()
493 mc->valid_cpu_types = valid_cpu_types; in mps2_an385_class_init()
494 mmc->scc_id = 0x41043850; in mps2_an385_class_init()
495 mmc->psram_base = 0x21000000; in mps2_an385_class_init()
496 mmc->ethernet_base = 0x40200000; in mps2_an385_class_init()
497 mmc->has_block_ram = true; in mps2_an385_class_init()
505 ARM_CPU_TYPE_NAME("cortex-m4"), in mps2_an386_class_init()
509 mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4"; in mps2_an386_class_init()
510 mmc->fpga_type = FPGA_AN386; in mps2_an386_class_init()
511 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); in mps2_an386_class_init()
512 mc->valid_cpu_types = valid_cpu_types; in mps2_an386_class_init()
513 mmc->scc_id = 0x41043860; in mps2_an386_class_init()
514 mmc->psram_base = 0x21000000; in mps2_an386_class_init()
515 mmc->ethernet_base = 0x40200000; in mps2_an386_class_init()
516 mmc->has_block_ram = true; in mps2_an386_class_init()
524 ARM_CPU_TYPE_NAME("cortex-m7"), in mps2_an500_class_init()
528 mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7"; in mps2_an500_class_init()
529 mmc->fpga_type = FPGA_AN500; in mps2_an500_class_init()
530 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7"); in mps2_an500_class_init()
531 mc->valid_cpu_types = valid_cpu_types; in mps2_an500_class_init()
532 mmc->scc_id = 0x41045000; in mps2_an500_class_init()
533 mmc->psram_base = 0x60000000; in mps2_an500_class_init()
534 mmc->ethernet_base = 0xa0000000; in mps2_an500_class_init()
535 mmc->has_block_ram = false; in mps2_an500_class_init()
543 ARM_CPU_TYPE_NAME("cortex-m3"), in mps2_an511_class_init()
547 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; in mps2_an511_class_init()
548 mmc->fpga_type = FPGA_AN511; in mps2_an511_class_init()
549 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in mps2_an511_class_init()
550 mc->valid_cpu_types = valid_cpu_types; in mps2_an511_class_init()
551 mmc->scc_id = 0x41045110; in mps2_an511_class_init()
552 mmc->psram_base = 0x21000000; in mps2_an511_class_init()
553 mmc->ethernet_base = 0x40200000; in mps2_an511_class_init()
554 mmc->has_block_ram = false; in mps2_an511_class_init()