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/linux-6.15/Documentation/devicetree/bindings/arm/
Darm,coresight-tmc.yaml24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
75 Indicates that the TMC-ETR can safely use the SG mode on this system.
100 description: AXI or ATB Master output connection. Used for ETR
106 - description: Reserved trace buffer memory for ETR and ETF sinks.
107 For ETR, this reserved memory region is used for trace data capture.
113 The default memory usage models for ETR in sysfs/perf modes are
119 - description: Reserved meta data memory. Used for ETR and ETF sinks
138 etr@20070000 {
Dqcom,coresight-ctcu.yaml16 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.
17 The configuration mode (ETB, ETF, ETR) is discovered at boot time when
21 It works as a helper device when connected to TMC ETR device.
23 the source device's Trace ID for TMC ETR device. The trace data with
24 that Trace id can get into ETR's buffer while other trace data gets
Darm,embedded-trace-extension.yaml19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
/linux-6.15/drivers/hwtracing/coresight/
Dcoresight-tmc.h123 /* TMC ETR Capability bit definitions */
125 /* ETR has separate read/write cache encodings */
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
141 /* TMC metadata region for ETR and ETF configurations */
146 uint32_t valid; /* Indicate if this ETF/ETR was enabled */
162 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
171 * struct etr_buf - Details of the buffer used by ETR
173 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
179 * @ops : ETR buffer operations for the mode.
225 * @etr_buf: details of buffer used in TMC-ETR
[all …]
Dcoresight-tmc-etr.c37 * etr_perf_buffer - Perf buffer used for ETR
38 * @drvdata - The ETR drvdaga this buffer has been allocated for.
39 * @etr_buf - Actual buffer used by the ETR
55 /* Convert the perf index to an offset within the ETR buffer */
59 /* Lower limit for ETR hardware buffer */
63 * The TMC ETR SG has a page size of 4K. The SG table contains pointers
108 * struct etr_sg_table : ETR SG Table
561 * tmc_init_etr_sg_table: Allocate a TMC ETR SG table, data buffer of @size and
847 * TMC ETR could be connected to a CATU device, which can provide address
849 * (ETR) connected to the input port of the CATU.
[all …]
Dcoresight-ctcu.h10 /* Maximum number of supported ETR devices for a single CTCU. */
16 * @port_num: in-port number of CTCU device that connected to ETR.
DKconfig41 trace router - ETR) or sink (embedded trace FIFO). The driver
54 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
55 buffer by translating the addresses used by ETR to the physical address
143 ETR device.
Dcoresight-ctcu-core.c29 * filter function based on the trace ID for each TMC ETR sink. The length of each
30 * ATID register is 32 bits. Therefore, an ETR device has a 128-bit long field
89 * @port_num: port number connected to TMC ETR sink.
Dcoresight-tmc-core.c610 * as ETR. in tmc_etr_can_use_sg()
694 /* Detect and initialise the capabilities of a TMC ETR */
721 * Unless specified in the device configuration, ETR uses a 40-bit in tmc_etr_setup_caps()
955 /* Coresight SoC 600 TMC-ETR/ETS */
1043 {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */
DMakefile32 coresight-tmc-etr.o
Dcoresight-catu.c80 * The base input address (used by the ETR, programmed in INADDR_{LO,HI})
313 * ETR started off at etr_buf->hwaddr. Convert the RRP/RWP to in catu_sync_etr_buf()
538 /* Default to the 40bits as supported by TMC-ETR */ in __catu_probe()
/linux-6.15/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc91 Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
92 mode. Writable only for TMC-ETR configurations. The value
99 Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available
101 for TMC ETR devices.
107 Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
108 only provide a mode which is supported for a given ETR device. This
109 file is available only for TMC ETR devices.
/linux-6.15/Documentation/devicetree/bindings/regulator/
Dmaxim,max8973.yaml74 maxim,enable-etr:
78 maxim,enable-high-etr-sensitivity:
82 sensitivity. If this property is available then etr will be enable
84 Enhanced transient response (ETR) will affect the configuration of CKADV.
137 maxim,enable-etr;
/linux-6.15/Documentation/trace/coresight/
Dpanic.rst37 For ETR sink devices, this reserved region will be used for both trace
53 Comparator --->External out --->CTI -->External In---->ETR/ETF stop
59 ETR/ETF/ETB register snapshot etc.
62 the ETR/ETF/ETB device nodes for this.
73 ETR sinks should have trace buffers allocated from reserved memory,
109 Sample commands for testing a Kernel panic case with ETR sink
141 #ETR Flush in from Channel 0
169 echo "ETR CTI config for $i"
179 4. Choose reserved buffer mode for ETR buffer::
355 ETR::
Dcoresight.rst111 TMC-ETR:
123 Funnel, replicator (intelligent or not), TMC-ETR
212 20070000.etr 20120000.replicator 220c0000.funnel
303 <file details> out:1 -> ../../../20070000.etr/tmc_etr0
326 <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0
/linux-6.15/drivers/accel/habanalabs/gaudi/
Dgaudi_coresight.c543 "ETR buffer address shouldn't exceed 50 bits\n"); in gaudi_etr_validate_address()
549 "ETR buffer size %llu overflow\n", size); in gaudi_etr_validate_address()
573 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); in gaudi_etr_validate_address()
603 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
610 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi_config_etr()
627 "ETR buffer size should be bigger than 0\n"); in gaudi_config_etr()
634 dev_err(hdev->dev, "ETR buffer address is invalid\n"); in gaudi_config_etr()
646 /* make ETR not privileged */ in gaudi_config_etr()
649 /* make ETR non-secured (inverted logic) */ in gaudi_config_etr()
917 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in gaudi_halt_coresight()
/linux-6.15/drivers/accel/habanalabs/goya/
Dgoya_coresight.c375 "ETR buffer size %llu overflow\n", size); in goya_etr_validate_address()
407 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
414 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in goya_config_etr()
429 "ETR buffer size should be bigger than 0\n"); in goya_config_etr()
443 /* make ETR not privileged */ in goya_config_etr()
445 /* make ETR non-secured (inverted logic) */ in goya_config_etr()
712 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in goya_halt_coresight()
/linux-6.15/drivers/crypto/intel/qat/qat_common/
Dadf_common_drv.h253 struct adf_bar *etr; in adf_get_etr_base() local
255 etr = &GET_BARS(accel_dev)[hw_data->get_etr_bar_id(hw_data)]; in adf_get_etr_base()
257 return etr->virt_addr; in adf_get_etr_base()
/linux-6.15/include/dt-bindings/memory/
Dtegra186-mc.h191 /* ETR reads */
193 /* ETR writes */
Dtegra194-mc.h211 /* ETR read clients */
213 /* ETR write clients */
/linux-6.15/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpsoc_etr_regs.h19 * (Prototype: ETR)
/linux-6.15/drivers/accel/habanalabs/include/goya/asic_reg/
Dpsoc_etr_regs.h18 * PSOC_ETR (Prototype: ETR)
/linux-6.15/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dpsoc_etr_regs.h18 * PSOC_ETR (Prototype: ETR)
/linux-6.15/drivers/accel/habanalabs/gaudi2/
Dgaudi2_coresight.c2155 dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size); in gaudi2_etr_validate_address()
2187 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); in gaudi2_etr_validate_address()
2217 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi2_config_etr()
2224 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", in gaudi2_config_etr()
2238 dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n"); in gaudi2_config_etr()
2243 dev_err(hdev->dev, "ETR buffer address is invalid\n"); in gaudi2_config_etr()
2258 /* make ETR not privileged */ in gaudi2_config_etr()
2260 /* make ETR non-secured (inverted logic) */ in gaudi2_config_etr()
2596 dev_err(hdev->dev, "halt ETR failed, %d\n", rc); in gaudi2_halt_coresight()
/linux-6.15/arch/arm64/boot/dts/arm/
Djuno-scmi.dtsi14 etr@20070000 {

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