hwtracing/coresight/coresight-tmc.h

123 /* TMC ETR Capability bit definitions */
125 /* ETR has separate read/write cache encodings */
137 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */
141 /* TMC metadata region for ETR and ETF configurations */
146 	uint32_t valid;         /* Indicate if this ETF/ETR was enabled */
162 	ETR_MODE_ETR_SG,	/* Uses in-built TMC ETR SG mechanism */
171  * struct etr_buf - Details of the buffer used by ETR
173  * @mode	: Mode of the ETR buffer, contiguous, Scatter Gather etc.
179  * @ops		: ETR buffer operations for the mode.
225  * @etr_buf:	details of buffer used in TMC-ETR
229  *		TMC-ETR on AXI bus.
233  * @etr_caps:	Bitmask of capabilities of the TMC ETR, inferred from the
235  * @idr:	Holds etr_bufs allocated for this ETR.
237  * @sysfs_buf:	SYSFS buffer for ETR.
238  * @perf_buf:	PERF buffer for ETR.
239  * @resrv_buf:  Used by ETR as hardware trace buffer and for trace data
244  *		 Used by ETR/ETF.
258 		struct etr_buf	*etr_buf;	/* TMC ETR */
333 /* ETR functions */