| /linux-6.8/drivers/gpu/drm/i915/display/ |
| D | intel_dsb.c | 48 * ins_start_offset will help to store start dword of the dsb
58 * DOC: DSB
60 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
61 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
62 * engine that can be programmed to download the DSB from memory.
65 * faster. DSB Support added from Gen12 Intel graphics based platform.
67 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
70 * DSB HW can support only register writes (both indexed and direct MMIO
71 * writes). There are no registers reads possible with DSB HW engine.
74 /* DSB opcodes. */
[all …]
|
| D | intel_dsb.h | 19 void intel_dsb_finish(struct intel_dsb *dsb);
20 void intel_dsb_cleanup(struct intel_dsb *dsb);
21 void intel_dsb_reg_write(struct intel_dsb *dsb,
23 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
25 void intel_dsb_noop(struct intel_dsb *dsb, int count);
26 void intel_dsb_nonpost_start(struct intel_dsb *dsb);
27 void intel_dsb_nonpost_end(struct intel_dsb *dsb);
29 void intel_dsb_commit(struct intel_dsb *dsb,
31 void intel_dsb_wait(struct intel_dsb *dsb);
|
| /linux-6.8/drivers/hwtracing/coresight/ |
| D | coresight-tpdm.c | 38 drvdata->dsb->edge_ctrl[tpdm_attr->idx]); in tpdm_simple_dataset_show()
43 drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
48 drvdata->dsb->trig_patt[tpdm_attr->idx]); in tpdm_simple_dataset_show()
53 drvdata->dsb->trig_patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
58 drvdata->dsb->patt_val[tpdm_attr->idx]); in tpdm_simple_dataset_show()
63 drvdata->dsb->patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
68 drvdata->dsb->msr[tpdm_attr->idx]); in tpdm_simple_dataset_show()
93 drvdata->dsb->trig_patt[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
99 drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
105 drvdata->dsb->patt_val[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
[all …]
|
| D | coresight-tpdm.h | 12 /* DSB Subunit Registers */
23 /* Enable bit for DSB subunit */
25 /* Enable bit for DSB subunit perfmance mode */
27 /* Enable bit for DSB subunit trigger type */
29 /* Data bits for DSB high performace mode */
31 /* Data bits for DSB test mode */
34 /* Enable bit for DSB subunit pattern timestamp */
36 /* Enable bit for DSB subunit trigger timestamp */
38 /* Bit for DSB subunit pattern type */
41 /* DSB programming modes */
[all …]
|
| /linux-6.8/Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-tpdm | 30 (RW) Set/Get the trigger type of the DSB for tpdm.
33 0 : Set the DSB trigger type to false
34 1 : Set the DSB trigger type to true
41 (RW) Set/Get the trigger timestamp of the DSB for tpdm.
44 0 : Set the DSB trigger type to false
45 1 : Set the DSB trigger type to true
52 (RW) Set/Get the programming mode of the DSB for tpdm.
66 (RW) Set/Get the index number of the edge detection for the DSB
103 Read a set of the edge control value of the DSB in TPDM.
110 Read a set of the edge control mask of the DSB in TPDM.
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
82 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
14 "PublicDescription": "Number of DSB to MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
22 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
27 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
30 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
63 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
72 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
14 "PublicDescription": "Number of DSB to MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
22 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
27 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
30 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
63 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
72 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
|
| /linux-6.8/arch/arm64/kvm/hyp/nvhe/ |
| D | tlb.c | 25 * CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN in __tlb_switch_to_guest()
31 * registers out of context, for which dsb(nsh) is enough in __tlb_switch_to_guest()
33 * The composition of these two barriers is a dsb(DOMAIN), and in __tlb_switch_to_guest()
39 dsb(nsh); in __tlb_switch_to_guest()
41 dsb(ish); in __tlb_switch_to_guest()
103 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
105 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
133 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
135 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
159 dsb(ish); in __kvm_tlb_flush_vmid_range()
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/skylake/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
35 "BriefDescription": "Retired Instructions who experienced DSB miss.",
41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
46 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
52 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
270 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias t…
274 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
|
| /linux-6.8/arch/arm64/kvm/hyp/vhe/ |
| D | tlb.c | 97 dsb(ishst); in __kvm_tlb_flush_vmid_ipa()
116 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
118 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
129 dsb(nshst); in __kvm_tlb_flush_vmid_ipa_nsh()
148 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
150 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
169 dsb(ishst); in __kvm_tlb_flush_vmid_range()
176 dsb(ish); in __kvm_tlb_flush_vmid_range()
178 dsb(ish); in __kvm_tlb_flush_vmid_range()
188 dsb(ishst); in __kvm_tlb_flush_vmid()
[all …]
|
| /linux-6.8/fs/erofs/ |
| D | super.c | 57 struct erofs_super_block *dsb; in erofs_superblock_csum_verify() local
63 dsb = kmemdup(sbdata + EROFS_SUPER_OFFSET, len, GFP_KERNEL); in erofs_superblock_csum_verify()
64 if (!dsb) in erofs_superblock_csum_verify()
67 expected_crc = le32_to_cpu(dsb->checksum); in erofs_superblock_csum_verify()
68 dsb->checksum = 0; in erofs_superblock_csum_verify()
70 crc = crc32c(~0, dsb, len); in erofs_superblock_csum_verify()
71 kfree(dsb); in erofs_superblock_csum_verify()
112 struct erofs_super_block *dsb) in check_layout_compatibility() argument
114 const unsigned int feature = le32_to_cpu(dsb->feature_incompat); in check_layout_compatibility()
164 struct erofs_super_block *dsb) in z_erofs_parse_cfgs() argument
[all …]
|
| /linux-6.8/Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-tpdm.yaml | 14 Single Bit (DSB). It performs data collection in the data producing clock
47 qcom,dsb-element-size:
49 Specifies the DSB(Discrete Single Bit) element size supported by
51 is enabled. DSB element size currently only supports 32-bit and 64-bit.
55 qcom,dsb-msrs-num:
57 Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
59 or set to 0, it means this DSB TPDM doesn't support MSR.
97 qcom,dsb-element-size = /bits/ 8 <32>;
98 qcom,dsb-msrs-num = <16>;
|
| /linux-6.8/arch/arm64/include/asm/ |
| D | tlbflush.h | 35 "dsb ish\n tlbi " #op, \
43 "dsb ish\n tlbi " #op ", %0", \
180 * DSB ISHST // Ensure prior page-table updates have completed
182 * DSB ISH // Ensure the TLB invalidation has completed
246 dsb(nshst); in local_flush_tlb_all()
248 dsb(nsh); in local_flush_tlb_all()
254 dsb(ishst); in flush_tlb_all()
256 dsb(ish); in flush_tlb_all()
264 dsb(ishst); in flush_tlb_mm()
268 dsb(ish); in flush_tlb_mm()
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
39 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
101 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
39 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
101 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/rocketlake/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
37 "BriefDescription": "Retired Instructions who experienced DSB miss.",
43 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
48 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
272 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
276 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
51 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
60 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
83 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
94 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = …
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
149 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se…
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/haswell/ |
| D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
51 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
60 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
83 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
94 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = …
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
149 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se…
[all …]
|